Fujitsu Corporation

Toshiro Sato

Shogo Fujimori

Yuji Suwa

Kazumasa Kobayashi

Hiroyuki Adachi

Atsushi Takeuchi

Kenji Nagase

Masaki Tosaka

Toshiaki Sato

Seiichi Saito

Yasuhiro Yamashita

Eiji Ohta

Yoshiyuki Iwakura

Kumiko Teramae

Kazunari Gotou

Toshinari Hayashi

Kunitoshi Yamamoto

Kazuyoshi Kanei

Hisoka Takao

A parameter calculating apparatus includes a signal generator that generates at least two input signals which each contain different frequency components; a signal inputting unit that inputs the input signals generated by the signal generator to respective ports of a test object at the same time; a frequency component deconstructing unit that deconstructs an output signal which is obtained by synthesizing the input signals input by the signal inputting unit and output from an output port into the frequency components; and a parameter calculator that calculates parameters which indicate transfer coefficients among ports of the test object based on output values of the frequency components obtained via the deconstruction performed by the frequency component deconstructing unit and on input values of the frequency components of the input signals input at the same time to a plurality of ports.

Parameter calculating apparatus and simulation apparatus

An analyzing apparatus includes a result-data storing unit that determines whether result data that is calculated as a result of analysis is restorable by linear interpolation. If the result data is determined to be unrestorable by the linear interpolation, the result-data storing unit stores the result data in a predetermined storage unit. Moreover, the analyzing apparatus includes a data restoring unit that reads the result data from the storage unit. The data restoring unit performs the linear interpolation using the result data acquired, thereby restoring the result data.

Analyzing apparatus and data storage method

An electronic circuit designing method and apparatus designs an electronic circuit by CAD, by generating design constraints with respect to the electronic circuit based on at least one of general layout and wiring information related to devices and wirings included in the electronic circuit, user requirements defined by a user, and user resources defined by the user, and urging an input to the user by displaying the design constraints.

Electronic circuit designing method apparatus for designing an electronic circuit, and storage medium for storing an electronic circuit designing method

Electronic circuit designing method and apparatus, and storage medium

In order to achieve augmentation of the accuracy in calculation of noise and augmentation of the accuracy in a noise check which is performed, for example, when an electronic circuit is designed and further realize significant reduction of the time required for a noise check and augmentation of the operation efficiency by reduction of the man-hours of a designer in a noise analysis, a noise checking apparatus includes a model production section () for producing a simulation model of a circuit portion relating to a noticed wiring line, a simulation section () for performing a simulation using the simulation model to calculate a signal waveform which propagates in the noticed wiring line and calculate a noise waveform superposed on the signal waveform for each kind of noise, a noise waveform synthesis section () for synthesizing the signal waveform and the noise waveforms with generation timings of the noise waveforms taken into consideration to obtain a noise composite waveform, and a noise checking section () for performing noise checking based on the noise composite waveform.

Noise checking method and apparatus

A crosstalk noise calculation method for calculating crosstalk noise among a plurality of wirings, includes calculating a crosstalk noise using a function in which the crosstalk noise becomes approximately constant when a predetermined wiring length is exceeded, so as to improve the design efficiency of the wirings by preventing an excessively strict checking from being performed.

Crosstalk noise calculation method and storage medium

Pin-scan-in type LSI logic circuit, pin-scan-in system driving circuit,

A logic circuit includes an inverter circuit including a first enhancement type field effect transistor having a gate connected to an input, and a first depletion type transistor having a gate and a source which are directly connected to a drain of the first enhancement type field effect transistor. A source follower circuit including a second enhancement type field effect transistor having a gate is connected to a connecting point of the first enhancement type field effect transistor and the first depletion type field effect transistor. A second depletion type field effect transistor having a gate and a source which are directly connected to each other has a drain which is connected to a source of the second enhancement type field effect transistor. A first power source is connected to the drains of the first depletion type field effect transistor and the second enhancement type field effect transistor and a second power source is connected to the sources of the first enhancement type field effect transistor and the second depletion type field effect transistor. An output is formed at the connecting point of the second enhancement type field effect transistor and the second depletion type field effect type transistor.

GaAs MESFET logic buffers using enhancement and depletion FETs

Growing community of inventors

Kawasaki, Japan

Toshiro Sato