Japan Science and Technology Agency

Mitsubishi Electric Corporation

Toshiba Electronic Devices & Storage Corporation

The University of Tokyo

Toshiro Hiramoto

Masaharu Kobayashi

Tomoko Matsudai

Kiyoshi Takeuchi

Shinichi Suzuki

Katsumi Satoh

Takuya Saraya

Kazuo Itou

Toshihiko Takakura

Fei Mo

Munetoshi Fukui

Jixuan Wu

A semiconductor device includes an emitter layer of a first conductivity type, a collector layer of a first conductivity type, a drift layer of a second conductivity type provided between the emitter layer and the collector layer, an emitter electrode electrically connected to the emitter layer, a collector electrode electrically connected to the collector layer, one or a plurality of emitter-side gate electrodes arranged to face the emitter layer with an emitter-side gate insulating film interposed therebetween, a first high-concentration impurity layer of a second conductivity type provided between the emitter electrode and the emitter layer, the first high-concentration impurity layer having an impurity concentration higher than an impurity concentration of the emitter layer, an impurity layer of a first conductivity type provided between the drift layer and the collector electrode, one or a plurality of collector-side gate electrodes arranged to face the impurity layer with a collector-side gate insulating film interposed therebetween, and a second high-concentration impurity layer of a second conductivity type provided between the collector electrode and the impurity layer and having an impurity concentration higher than that of the impurity layer, in which a total length of a first facing region of the emitter-side gate electrode in a gate width direction, the first facing region facing the emitter layer with the emitter-side gate insulating film interposed therebetween, is longer than a total length of a second facing region of the collector-side gate electrode in a gate width direction, the second facing region facing the impurity layer with the collector-side gate insulating film interposed therebetween.

Semiconductor device

A three-dimensional array device with multiple layers in height direction includes a first two-dimensional array circuit located in a first layer; and a second two-dimensional array circuit located in a second layer adjacent to the first layer and overlapped in a plan view with the first two-dimensional array circuit. Each of the first two-dimensional array circuit and the second two-dimensional array circuit has a first wiring group, an input part that inputs signals to the first wiring group, a second wiring group that intersects the first wiring group and an output part that outputs signals from the second wiring group. The output part in the first two-dimensional array circuit is overlapped in a plan view on the input part in the second two-dimensional array circuit and is connected in a signal transferable manner.

Three-dimensional array device

A ferroelectric memory device comprising a plurality of ferroelectric memory elements. Each of the plurality of ferroelectric memory elements includes a channel layer containing a metal oxide, a ferroelectric layer in contact with the channel layer in which the ferroelectric layer contains hafnium oxide, a first gate electrode facing the channel layer via the ferroelectric layer, an insulating layer facing the ferroelectric layer via the channel layer; and a second gate electrode facing the channel layer via the insulating layer.

Ferroelectric memory device and operation method thereof

Growing community of inventors

Tokyo, Japan

Toshiro Hiramoto