Fujitsu Corporation

Fujitsu Semiconductor Limited

Toshiro Futatsugi

Naoki Yokoyama

Naoto Horiguchi

Haruo Kawata

Toshio Oshima

Tsukasa Onodera

Toshihiko Mori

Tetsuzo Yoshimura

Tatsuya Usuki

Kenichi Imamura

Toshio Fujii

Kenichi Hikazutani

Akihiro Shibatomi

Ken-ichi Okabe

Kazuaki Ishii

The semiconductor variable capacitor includes a capacitor including an n-wellformed in a first region of a semiconductor substrate, an insulating filmformed over the semiconductor substrateand a gate electrodeformed above the n-wellwith the insulating filminterposed therebetween; and a p-wellof a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate. The gate electrodehas an end which is extended to the second region and formed above the p-wellwith the insulating filminterposed therebetween.

Semiconductor variable capacitor and method of manufacturing the same

A method of manufacturing semiconductor device comprising forms a first impurity diffusion region as a lower electrode of a capacitor in a first area of a semiconductor substrate by implanting impurities at a first dose; forms a second impurity diffusion region in a second area, at the end part of the semiconductor substrate, by implanting impurities at a second dose; and forms, by a thermal oxidation method, a capacitor insulation film having a first thickness on the first impurity diffusion region and forms an oxide film having a second thickness which is thicker than the first thickness on the second area.

Method of manufacturing semiconductor device

A non-volatile semiconductor memory comprising a semiconductor substrate, a gate insulating film formed on the substrate, and having a thin central section and thick end sections, a floating gate formed on the rate insulating film, an inter-electrode insulating film formed on the floating gate, a control gate formed on the inter-electrode insulating film, and source/drain regions formed in the substrate on both sides of the floating sate and having extensions extending under the thick end sections of the floating gate, and separated from the thin central section of the gate insulating film, wherein the thin central section enables tunneling of carriers at a low applied voltage, and thick end sections prevent tunneling of stored charges to the extensions and enhance retention of the stored charges.

Non-volatile semiconductor memory device having gate insulating film with thick end sections

A semiconductor memory device having a plurality of memory cells, word lines and bit lines formed on a semiconductor substrate, where each of the memory cells includes a source area formed adjacent to a channel area in the semiconductor substrate; a drain area formed opposite the source area with the channel area therebetween in the semiconductor substrate, the drain area being connected to one of the bit lines; a tunnel insulating film formed on the channel area, the tunnel insulating film having a proper thickness for a carrier to pass through by a tunnel phenomenon; a floating gate formed on the tunnel insulating film so as to overlap neither the source area nor the drain area; a gate insulating film formed on the floating gate so as to cover the floating gate; and a control gate formed on the gate insulating film so as to partially overlap both of the source area and the drain area, the control gate being connected to one of the word lines. In the semiconductor memory device, the source areas of the memory cells are connected to each other so that a common voltage is supplied to each of the source areas.

Semiconductor memory device having source areas of memory cells supplied with a common voltage

A non-linear optical device includes a plurality of quantum dots in an active layer such that the quantum dots have a composition or doping modified asymmetric in a direction perpendicular to the active layer.

Non-linear optical device using quantum dots

A source region and a drain region are formed in a surface layer of a semiconductor substrate on both sides of a channel region defined in the surface layer. A tunneling insulating film is formed on the channel region, the tunneling insulating film having a thickness which allows carriers to tunnel therethrough. A floating gate electrode is formed on the tunneling insulating film, the floating gate electrode being disposed so as to overlap neither the source region nor the drain region as viewed along a substrate normal direction. A gate insulating film is formed over the channel region, covering the floating gate electrode. A control gate electrode is formed on the gate insulating film, the control gate electrode being disposed so as to become in contact with, or partially overlap, the source and drain regions as viewed along the substrate normal direction. Materials of the floating gate electrode and channel region are selected so that a Fermi level of the floating gate electrode is positioned in an energy band gap of the channel region when an external voltage is not applied between the channel region and the control gate electrode.

Semiconductor memory with floating gate type FET

A semiconductor quantum dot device using a semiconductor quantum dot comprises a semiconductor quantum dot formed on a semiconductor wafer, a field effect transistor formed on said semiconductor wafer and comprising a gate electrode formed in a vicinity of said semiconductor quantum dot, and a coupling means to couple said gate electrode and said semiconductor quantum dot capacitively.

Semiconductor quantum dot device

A semiconductor device comprises stacked first through fifth semiconductor layers. The semiconductor device has an energy level condition of .vertline.Ec.sub.3 -Ec.sub.1 .vertline..apprxeq..vertline.Ev.sub.3 -Ev.sub.5 .vertline., where Ec.sub.3 is a resonant energy level of electrons in a conduction band of the third layer and Ev.sub.3 is a resonant energy level of holes in a valence band thereof, and Ec.sub.1 is an energy level of a conduction band of the first layer and Ev.sub.5 is an energy level of a valence band of the fifth layer.

Semiconductor device

A semiconductor memory device comprises a transistor having such a current characteristic that a base current has a differential negative resistance characteristic and a collector current greatly flows after the differential negative resistance characteristic occurs in the base current when a base-emitter voltage is increased, a load coupled in series between a collector and a base of the transistor, first and second input terminals coupled to the base of the transistor through a base resistance of the transistor, and an ouptut terminal coupled to the collector of the transistor.

Semiconductor memory device using resonant-tunneling transistor

An electrode structure of an electrode of a refractory metal or a silicide thereof on a layer of In.sub.x Ga.sub.1-x As (0&lt;x&lt;1) on a substrate of a III-V compound semiconductor is ohmic and is stable even at a high temperature, for example, 900.degree. C. This high temperature stable ohmic electrode structure allows ion implantation into the substrate with the electrode as a mask followed by annealing to form a doped region in alignment with the edge of the electrode.

Method of forming a high temperature stable ohmic contact to a III-V

A semiconductor device comprises a first barrier layer, a quantum well layer formed on the first barrier layer and having a bottom of conduction band with an energy which varies with a curve of second order, a second barrier layer formed on said quantum well layer, and first and second contact layers. The first barrier layer, the quantum well layer and the second barrier layer make up a layer sequence which is repeated a predetermined number of times, and the first contact layer connects to the first barrier layer in a first of the predetermined number of layer sequences, while the second contact layer connects to the second barrier layer in a last of the predetermined number of layer sequences.

Semiconductor device utilizing multiquantum wells

In a semiconductor integrated circuit device, a plurality of a field effect transistors are formed on a (110) crystal surface of a group III-V compound semiconductor substrate having a zinc blend type crystal structure.

Semiconductor integrated circuit device

An IC device comprising a plurality of FET's using a compound semiconductor, more specifically, a zincblende type semiconductor substrate, having a surface of a (111) plane. By use of this plane, differences of characteristics of the FET's depending on directions along which gates of the FET's are arranged when the gate length is made shorter are prevented, allowing arrangement of gates of the FET's in different directions, particularly perpendicular to each other, with making the gate length shorter to miniaturize and densify the device.

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Kawasaki, Japan

Toshiro Futatsugi