Fujitsu Corporation

Nippon Oil Company

Nippon Oil Corporation

Nec Mobiling, Ltd.

Jx Nippon Oil Energy Corporation

Toshio Yoshida

Takashi Suzuki

Shozaburo Konishi

Hajime Nakao

Hideo Yokota

Ken Sawada

Hiroyuki Hoshino

Yuji Shimomura

Kazuo Tagawa

Katsuya Takigawa

Satoshi Suda

Yasunobu Akizuki

Masahiro Hata

Eiji Akiyama

Junichi Shibata

Shinichi Mitsumoto

Jinichi Igarashi

Ryuji Kan

Mikio Hondou

Harumichi Watanabe

Yoko Matsuyama

Masaki Ukai

Shuji Yamamura

Ryuichi Sunayama

Naohiro Kiyota

Atsushi Fusejima

Tomonari Yomoda

Iwao Yamazaki

Masaru Ushio

Tomohiro Tanaka

Yutaka Shikatani

Norihito Gomyo

Hideo Yamashita

Hiroyuki Takashima

Mitsuo Okada

Sota Sakashita

Masakuni Hirata

Tsuyoshi Motokurumada

Mikio Hondo

Masaharu Maruyama

Mariko Sakamoto

Susumu Akiu

Yoshiaki Nagai

Kouzou Kamiya

Isao Honjo

Yuji Ikemoto

Kouichi Oshima

Mitsuhiko Takei

Koji Masamizu

A Load and Store Queue (LDSTQ) stores load store instructions therein with an upper limit being a first number, and sequentially outputs the stored load store instructions to cause a data cache or a main memory to execute processing of data in accordance with the output load store instructions. A decode unit acquires load store instructions, and determines a queued number of load store instructions which have not been output from the LDSTQ among load store instructions output from the decode unit. When the queued number is smaller than a second number which is larger than the first number, the decode unit outputs the acquired load store instructions. An LDSTQ management unit acquires the output load store instructions. When the stored number of load store instructions stored in the LDSTQ is smaller than the first number, the LDSTQ management unit stores the acquired load store instructions in the LDSTQ.

Arithmetic processing device and method of controlling arithmetic processing device

An arithmetic processing apparatus includes a decoder, a first cache memory, a second cache memory and a processor. The processor performs a cache hit determination on the first cache memory in response to a memory access instruction, issues a data request to a second cache memory when the cache hit determination is a cache miss. When the memory access instruction is for a speculative execution speculatively executed in a state where a branch destination of a branch instruction is unestablished, the decoder issues the memory access instruction with a valid prohibition flag and an instruction identifier. In a case where the cache hit determination is the cache miss and the prohibition flag is valid, the processor does not issue the data request to the second cache memory. In a case where the cache hit determination is a cache hit, the processor acquires data from the first cache memory.

Arithmetic processing apparatus and control method for arithmetic processing apparatus

An arithmetic processing device having an allocation unit configured to reserve a memory allocation area in a memory and register address range information indicating an address range of the memory allocation area in an address range table, in response to an execution of a memory area allocation function requesting memory area allocation, and a determination unit configured to refer to the address range table and perform determination processing as to whether or not an access destination address of a memory access instruction is within an address range indicated by the address range information registered in the address range table, in response to an execution of the memory access instruction relating to the memory allocation area.

Arithmetic processing device, information processing device, control method for information processing device, and control program for information processing device

A lubricating oil composition comprising a lubricating base oil, and a mixture and/or a reaction product of (A) 0.01-0.5% by mass of at least one compound selected from among acid phosphates represented by formula (1) or formula (2), and (B) 0.01-2% by mass of an alkylamine represented by formula (3), based on the total weight of the composition, wherein the acid value due to component (A) is 0.1-1.0 mgKOH/g. [Rand Rrepresent hydrogen or straight-chain alkyl or straight-chain alkenyl groups, with at least one of Rand Rbeing a C6-12 straight-chain alkyl or straight-chain alkenyl group; Rand Rrepresent hydrogen straight-chain alkyl or straight-chain alkenyl groups, with at least one of Rand Rbeing a C13-18 straight-chain alkyl or straight-chain alkenyl group; and Rand Rrepresent hydrogen or C4-30 branched-chain alkyl groups, with at least one of Rand Rbeing a branched-chain alkyl group.] 

Lubricant composition

A processing apparatus comprising a register that stores operand data, a register data reading section that reads operand data stored in the register, a coefficient table set storage section that stores a coefficient table storing Taylor series operation coefficient data, a coefficient data reading section that reads the Taylor series coefficient data from the coefficient table set storage section using the degree information of the Taylor series and the coefficient table identification information and a floating point multiply-adder that executes the Taylor series operation using the coefficient data read by the coefficient data reading section, data read from the register.

Processing apparatus and control method performing taylor series operation associated with executing floating point instruction

A processor includes a storage unit storing an instruction, an instruction extension information register that includes a first area and a second area, an instruction decoding unit that decodes a first prefix instruction including first extension information extending an immediately following instruction written to the first area when the first prefix instruction is executed, and that decodes a second prefix instruction including the first extension information and a second extension information extending an instruction immediately following two instructions of the second prefix instruction, an instruction packing unit that generates a packed instruction including at least one of the first prefix instruction or the second prefix instruction, and the instruction immediately following the first prefix instruction or the second prefix instruction when the instruction decoding unit decodes the first prefix instruction or the second prefix instruction, an instruction execution unit that executes the packed instruction generated by the instruction packing unit.

Extended register addressing using prefix instruction

A cache memory having a sector function, operating in accordance with a set associative system, and performing a cache operation to replace data in a cache block in the cache way corresponding to a replacement cache way determined upon an occurrence of a cache miss comprises: storing sector ID information in association with each of the cache ways in the cache block specified by a memory access request; determining, upon the occurrence of the cache miss, replacement way candidates, in accordance with sector ID information attached to the memory access request and the stored sector ID information; selecting and outputting a replacement way from the replacement way candidates; and updating the stored sector ID information in association with each of the cache ways in the cache block specified by the memory access request, to the sector ID information attached to the memory access request.

Cache memory having sector function

The information processing device in the simultaneous multi-threading system is operated in an inter-thread performance load arbitration control method, and includes: an instruction input control unit for sharing among threads control of inputting an instruction in an arithmetic unit for acquiring the instruction from memory and performing an operation on the basis of the instruction; a commit stack entry provided for each thread for holding information obtained by decoding the instruction; an instruction completion order control unit for updating the memory and a general purpose register depending on an arithmetic result obtained by the arithmetic unit in an order of the instructions input from the instruction input control unit; and a performance load balance analysis unit for detecting the information registered in the commit stack entry and controlling the instruction input control unit.

Inter-thread load arbitration control detecting information registered in commit stack entry units and controlling instruction input control unit

A priority circuit is connected to a reservation station and a plurality of arithmetic units that processes different operations and dispatches, when it is determined that an executable flag indicating that an instruction can be executed by only a specific arithmetic unit is on, an instruction to an arithmetic unit that is different from the specific arithmetic unit and of which a queue is vacant in accordance with the input performed by an instruction decoder and the reservation station.

Dispatching instruction from reservation station to vacant instruction queue of alternate arithmetic unit

A plurality of register windows in a multithread processor are each provided for a corresponding thread and capable of storing data to be used for instruction processing in an arithmetic unit. A work register in the multithread processor is capable of mutually transferring data with respect to the register windows and the arithmetic unit. A multithread control unit in the multithread processor controls data transfer among the register windows, the work register and the arithmetic unit on the basis of an execution thread identifier identifying the thread to be executed in the arithmetic unit. This enables conducting the multithread processing at a high speed.

Multithread processor and method of controlling multithread processor

Multiple data processing instructions instruct a computing device to process multiple data including first data and second data. When a multiple data processing instruction is decoded, two allocatable registers are selected. One is used to store the result of a processing operation performed on first data by one processing unit, and the other is used to store the result of a processing operation performed on second data by another processing unit. Those stored processing results are then transferred to result registers. Normal data processing instructions, on the other hand, instruct a processing operation on third data. When a normal data processing instruction is decoded, one allocatable register is selected and used to store the result of processing that a processing unit performs on the third data. The stored processing result is then transferred to a result register.

Allocating rename register from separate register sets for each result data of multiple data processing instruction

A single-precision floating-point data storing method for use in a processor including a register, which has a size that can store double-precision floating-point data, for storing double-precision floating-point data and single-precision floating-point data comprises writing input single-precision floating-point data to the high-order half of the register, and writing all zeros to the low-order half of the register if a single-precision floating-point data process is specified.

Single precision floating-point data storing method and processor

An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic deviceincludes: an instruction execution circuitcapable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuitinstructing the instruction execution circuitto switch a thread mode.

Arithmetic device for processing one or more threads

The present invention provides a refrigerating machine oil, a compressor oil composition, a hydraulic oil composition, a metalworking oil composition, a heat treating oil composition, a lubricating oil composition for machine tools and a lubricating oil composition which comprise a lubricating oil base oil having % Cof not more than 2, % C/% Cof not less than 6 and an iodine value of not more than 2.5.

Compressor oil composition

A processing unit has an extended register to which instruction extension information indicating an extension of an instruction can be set. An operation unit that, when instruction extension information is set to the extended register, executes a subsequent instruction following a first instruction for writing the instruction extension information into the extended register, extends the subsequent instruction based on the instruction extension information.

Processor decoding extension instruction to store plural address extension information in extension register for plural subsequent instructions

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Kawasaki, Japan

Toshio Yoshida