Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Electric Co., Ltd.

Kabushiki Kaisha Toshiba

Other

Kanto Chemical Co., Inc.

Toyko Shibaura Electric Co., Ltd.

Toshio Yonezawa

Takashi Ajima

Shunichi Hiraki

Masaharu Aoyama

Yutaka Koshino

Masahiro Abe

Kuniaki Kumamaru

Hidekuni Ishida

Jiro Ohshima

Kouichi Takahashi

Hatsuo Nakamura

Seiji Yasuda

Shigeo Koguchi

Tiharu Kato

Masafumi Miyagawa

Masato Uchida

Yoshitami Oka

Kiyoshi Takaoki

Hisashi Muraoka

Kiyoto Mori

Akihito Nishikawa

Hiroshi Kinoshita

Toshihiro Abe

Shoichi Kitane

Toshio Mitsuno

Yoshihiro Motowaki

Jiro Oshima

Masahiko Igarashi

Disclosed herein are a product design process and apparatus for quickly and easily defining an optimal product concept capable of conveying a high degree of customer satisfaction. In the process of the present invention, wants and needs information is analyzed, and, based on the analyzed wants and needs information, weighting is carried out with respect to evaluation indices which have been previously stored in a storage device and which are quantitative measures of the degree to which the user is likely to perceive a benefit latent in the product under consideration and inherent in the wants and needs information to have been achieved, an evaluation index having the highest weighting among a plurality of weighted evaluation indices is selected as a primary evaluation index and a product design concept for which the primary evaluation index selected is a maximum or minimum is defined.

Product design process and product design apparatus

A method of manufacturing a semiconductor device by forming an N type collector layer in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorous and arsenic. Arsenic or antimony or the like, which are N type impurity material of which the energy of combination with vacancies is great are diffused in the P type base layer.

Method of manufacturing a bipolar transistor

A semiconductor device comprising an N type collector layer formed in an N type semiconductor wafer, a P type base layer which is in contact with the N type collector layer at a PN junction that extends to the surface and which contains an N type impurity material of which the energy of combination with vacancies is great and boron which is a P type impurity material, and an N type emitter layer which is so formed as to be surrounded by this P type base layer and forms a transistor together with the N type collector layer and the P type base layer and which contains the N type impurity materials phosphorus and arsenic. Arsenic or antimony or the like, which are N type impurity materials of which the energy of combination with vacancies is great are diffused in the P type base layer.

NPN transistor with base double doped with arsenic and boron

A semiconductor device with a bonding section comprising a semiconductor substrate, a silicon layer formed on the semiconductor substrate with a first insulating layer interposed therebetween, and a bonding pad formed on the silicon layer with a second insulating layer interposed therebetween. The silicon layer has substantially the same size as the bonding pad. When a lead line is bonded to the bonding pad, the silicon layer lessens the stress caused by the bonding.

Semiconductor device with an improved bonding section

A semiconductor device having a multilayer wiring structure which comprises a semiconductor substrate, a first wiring layer deposited on said substrate, and a second wiring layer deposited on said first wiring layer with insulating layers disposed therebetween, wherein the insulating interlayer consists of an inorganic insulating layer and a polyimide-based resin film overlying the inorganic insulating layer. The thickness ratio of the polyimide-based resin film to the inorganic insulating film ranges from 0.1 to 0.5. A method of manufacturing a semiconductor device of a multilayer wiring structure wherein an opening is formed in the insulating interlayer to have a small step.

Semiconductor device having a multilayer wiring structure using a

A method of dicing a semiconductor wafer in which a physical discontinuity is formed on the surface of the wafer on both sides of a dicing line to limit the spreading of cracks and chips generated during dicing. Thereafter, the semiconductor wafer is diced to separate the pellets.

Method of dicing a semiconductor wafer

A process tube that is impermeable to impurities for use in the manufacture of semiconductor devices. The process tube is made of sintered silicon carbide and it may optionally be infiltrated with elemental silicon. The inner surface of the process tube includes a layer of high density silicon carbide to prevent diffusion of impurity species through the walls of the process tube.

Apparatus for producing a semiconductor device

A semiconductor device comprising a high voltage withstanding vertical MOSFET and a low voltage withstanding element both formed on a single chip. A buried layer of a high impurity concentration is formed in a region where the vertical MOSFET is formed, and another buried layer of a high impurity concentration is formed in a region where the low voltage withstanding element is formed. These buried layers have different thickness, whereby the series resistance of a circuit adjacent to the vertical MOSFET is reduced without lowering the withstand voltage of the vertical MOSFET.

Semiconductor device monolithically comprising a V-MOSFET and bipolar

A method of manufacturing a semiconductor device wherein a pair of grooves having different depths are formed in a surface of a semiconductor substrate, an epitaxial layer of one conductivity type is grown to a depth enough to fill a shallower one of the grooves, and an epitaxial layer of the opposite conductivity type is further grown to a depth enough to fill a deeper one of the grooves, followed by the step of etching the entire surface to expose the surface of said semiconductor substrate and to leave in each groove an epitaxial layer of mutually different conductivity type and having the same depth and width. A semiconductor device as manufactured by the above method.

Semiconductor device and method for manufacturing the same

A method of manufacturing a semiconductor device which comprises the step of applying a silicon carbide film having a prescribed perforated pattern as a masking film selectively to etch a silicon dioxide film or diffuse an impurity into a substrate.

Method of manufacturing a semiconductor device

A semiconductor device is disclosed which includes a semiconductor substrate; a metal wiring layer comprising an Al alloy formed on the surface of this substrate; and an alumina layer covering this metal layer and containing at least one metal selected from the group consisting of Cu, Mg, Ni, Cr, Mn, Ti and Y. A method for manufacturing such a semiconductor device is also disclosed.

Semiconductor device

A semiconductor device comprising a substrate means, a semiconductor layer of an N conductivity type formed on the substrate means, a first semiconductor region of a P conductivity type formed in the semiconductor layer and having its exposed major surface, a second semiconductor region of the N conductivity type formed in the first semiconductor region and having its exposed major surface, a first insulation layer means having a positive polarity type of charge and formed on the N semiconductor layer, and a second insulation layer means having a negative polarity type of charge and formed on the P semiconductor region.

Semiconductor device with multi-layered structure

There is proposed a negative-working photoresist coating composition of an improved resolution, which comprises a cyclized polyisoprene having a weight-average molecular weight of 10,000 to 100,000 and a molecular weight distribution of not more than 1.9, an organic solvent of the cyclized polyisoprene, and a bisazido compound as a crosslinking agent.

Negative-working photoresist coating composition

A process for producing a semiconductor device by which the minority carrier lifetime can be selectively changed in a semiconductor device. A radiation beam is irradiated onto the surface of a semiconductor substrate to shorten the minority carrier lifetime. Then ions are selectively implanted into a region in which the minority carrier lifetime is to be recovered. Finally, the resultant structure is annealed.

Method of making integrated devices having long and short minority

A metallization structure having a substantially flat surface can be formed on a semiconductor substrate by forming first and second insulating layers on the substrate. The second insulating layer is selectively removed to form grooves therein. Then, a metallic material layer is conformably formed. The metallic layer has grooves corresponding to the grooves of the second insulating layer. A flowable polymer is applied to the surface of the resultant structure to form a layer having a flat surface. The polymer layer and the metallic layer are sequentially ion-etched to expose the second insulating layer. Thus, the metallization structure constituted by the remaining metallic layer and the second insulating layer is formed to have a flat surface.

Growing community of inventors

Yokosuka, Japan

Toshio Yonezawa