Matsushita Electric Industrial Co., Ltd.

Matsushita Electronics Corporation

Santex Co. Ltd.

Toshio Yamada

Masashi Agata

Michihiro Inoue

Akinori Shibayama

Hironori Akamatsu

Shunichi Iwanari

Hisakazu Kotani

Atsushi Fujiwara

Hirohito Kikukawa

Akihiro Sawada

Hiroyuki Yamauchi

Shin Hashimoto

Isao Miyanaga

Ichiro Nakao

Yasushi Okuda

Yoshirou Nakata

Yukiharu Uraoka

Kenzou Hatada

Shinji Odanaka

Yoshiro Nakata

Genshu Fuse

Kazuhiro Matsuyama

Masaki Fukumoto

Junko Hasegawa

Naoki Kuroda

Tsutomu Fujita

Susumu Matsumoto

Kazunari Takahashi

Hideya Esaki

Masahi Agata

In order to enhance the sensitivity of a sense amplifier circuit, each one of the transistor pair composing the sense amplifier circuit is formed by transistors connected parallel in an even number of stages, and therefore the sense amplifier circuit is made of transistor pair having an extremely balanced characteristic, cancelling the asymmetricity of current-voltage characteristic of the transistor pair to null.

Sense amplifier circuit

A plurality of information memory cells and a single reference memory cell are coupled to a single word line. The reference memory cell stores reference information equivalent to a reference potential to information readout. Pieces of information, stored in the information memory cells, are fed, over respective bit lines, to first input terminals of sense amplifiers. The reference information, stored in the reference memory cell, is fed, over a bit line, to second input terminals of the sense amplifiers. When the potential of signal charges stored in the information memory cells falls due to leakage current, the potential of a signal charge stored in the reference memory cell correspondingly falls due to leakage current. This prolongs a length of time taken for a difference between these potentials to reach a sense limit, thereby achieving a longer data retention time. As a result of such arrangement, even when there occurs a small current leakage from memory cells, it is possible to secure a long data retention time thereby making it possible to obtain a long refresh cycle period.

Semiconductor memory

A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.

Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method

A timing signal generation circuit according to the present invention includes: a delay circuit for transmitting an input clock signal while delaying the clock signal, the delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the delay circuit; a detection delay circuit for transmitting the clock signal while delaying the clock signal, the detection delay circuit having a plurality of intermediate taps capable of outputting the clock signal at their corresponding positions in the detection delay circuit; a plurality of sample/hold circuits each having a sampling signal terminal, the sampling signal terminals being connected to corresponding ones of the plurality of intermediate taps of the detection delay circuit; a plurality of boundary delay circuits for detecting an edge of the clock signal, the boundary detection circuits being connected to respective output terminals of the sample/hold circuits; and an output selection circuit for extracting the clock signal via at least one of the plurality of intermediate taps selected in accordance with an edge position of the clock signal detected by the boundary detection circuits, the output selection circuit outputting the extracted clock signal as a timing signal.

Timing signal generation circuit

The semiconductor storage device of this invention includes memory cells each having two transistors and one storage capacitor. Each memory cell is connected with a first word line and a first bit line for a first port and a second word line and a second bit line for a second port. The first and second bit lines are alternately disposed in an open bit line configuration. In the operation of the semiconductor storage device, in a period when a first precharge signal for precharging each first bit line or a first sense amplifier activating signal for activating a first sense amplifier is kept in an active state, a second precharge signal for precharging each second bit line and a second sense amplifier activating signal for activating a second sense amplifier are both placed in an inactive state.

Semiconductor storage device

A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator. Since Vint is generated based on the two outputs Vref and Vrefbi which are outputted from the single reference voltage generator and which are related to each other, the power consumption and layout area of an internal reduced-voltage generator, which is suitable for the burn-in, can be reduced.

Internal reduced-voltage generator for semiconductor integrated circuit

Semiconductor wafer package, method and apparatus for connecting testing

A CPU acting as a mother chip, in combination with a DRAM acting as a subsidiary chip, is mounted. A mode output circuit is able to set the storage capacity of the DRAM as well as the refresh cycle of the DRAM for forwarding to a mode input circuit of the CPU through a mode output terminal of the DRAM and a mode input terminal of the CPU. The CPU controls an address generator according to the data from the mode input circuit, to set the number of bits of address data for access to the DRAM according to the DRAM storage capacity and the DRAM refresh cycle.

Semiconductor integrated circuit having a plurality of chips

In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

Data transmission circuit, data line driving circuit, amplifying

A first p-type transmission MOS transistor with a gate connected to one of complementary input signal lines, a source connected to a first power supply and a drain connected to one of complementary output signal lines, is provided. A second p-type transmission MOS transistor with a gate connected to the other of the complementary input signal lines, a source connected to the first power supply and a drain connected to the other of the complementary output signal lines, is provided. A first capacitive element is connected between the gate and substrate of the first transmission MOS transistor. A second capacitive element is connected between the gate and substrate of the second transmission MOS transistor. At the time when signals are transmitted, the substrate voltage of the transmission MOS transistor is changed statically in synchronization with the input signal. As a result of such arrangement, the threshold voltage of the transmission MOS transistors can be regulated to be high in the standby state and can be regulated to be low in the active state. Therefore, the control of leakage current becomes possible in the standby state and the drain current increases in the active state thereby providing a high signal transmission rate.

Transmission circuit

Growing community of inventors

Osaka, Japan

Toshio Yamada