Hitachi, Ltd.

Nippon Steel Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Topcon Corporation

Max Co., Ltd.

Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Hitachi Vlsi Engineering Corp.

Hitachi Ulsi Engineering Corp.

Fujimori Kogyo Co., Ltd.

Hitachi Computer Engineering Co., Ltd.

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Hokkai Semiconductor Ltd.

Toshio Yamada

Yuichi Sato

Tohru Kobayashi

Masato Hamamoto

Kazuo Tanaka

Hiromasa Katoh

Yoshio Takazawa

Atsushi Shimizu

Mitsuo Usami

Hiroaki Sakamoto

Noboru Shiozawa

Kazumasa Yanagisawa

Hirotaka Nishizawa

Toshio Sasaki

Nobuyuki Nishita

Hiroyuki Itoh

Tatsuya Kimura

Akira Masaki

Takeo Kanai

Tsutomu Ozawa

Shinichi Ozawa

Kaoru Koyu

Kazuyoshi Satoh

Minoru Katoh

Koudou Yamauchi

Toshihiro Araki

Michinobu Mizumura

Akira Shimase

Akinobu Watanabe

Satoshi Yanobe

Ryo Mori

Masayoshi Yagyu

Fumikazu Itoh

Satoshi Haraichi

Takashi Hayasaka

Junzou Azuma

Masahiro Fujikura

Yasuhiro Koizumi

Yuuichi Hamamura

Tetsuya Muraya

Atsushi Doji

Kiyoshi Inoue

Toshio Sugano

Kazuki Osaragi

Masamichi Ishihara

Hidetoshi Iwai

Yasunori Yamaguchi

Wataru Ohashi

Yoshiharu Inoue

Sadayuki Matsumoto

Akihisa Uchida

Takeo Saikatsu

Jiro Sawada

Michiaki Adachi

Masahiro Yamamura

Seiichiro Tsukui

Masami Kobayashi

Akihiko Fujimoto

Junichiro Hoshizaki

Tadao Kaji

Satoshi Yamashita

Yoshihiro Shinozaki

Keijiro Murayama

Mikinori Kawaji

Yuko Ito

Takehiko Sakurai

Mitsunobu Abe

Osamu Myodo

Takayuki Yoshitake

Takashi Araki

Tatsuya Saitoh

Hidetomo Aoyagi

Hideo Shingu

Shinobu Takeura

Noriyasu Kiryuu

Norihiko Kasai

Mitsuhiro Takatsuru

Chiemi Hashimoto

Ichirou Anjou

Seiichiro Azuma

Hideki Okushima

Sukehiro Yoshida

Sinmei Hirano

Yasusi Sekine

Hideo Hagiwara

Fumio Hasebe

Hiromi Chida

Hisae Nishimatsu

Kazuo Yoshika

Hrumi Sawada

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Hiroyuki Ikeda

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

Hiroyuki Itho

Keiziro Murayama

An external controller specifies the direction of a surveying instrument with respect to a laser marking instrument to calculate a first relative angle as an angle relative to the surveying instrument, calculates a second relative angle as an angle relative to a target line based on design information, and calculates a differential angle between the first relative angle and the second relative angle, thereby rotating a marking laser emitter by the differential angle to project marking laser light onto the target line.

Marking system and marking method

The present management system includes a design database recording member identification information and member shape information on construction members constituting a construction object, a measurement database recording point coordinates of measurement points of the construction object, a member shape information acquiring unit configured to acquire the member shape information of a shape calculation member selected among the construction members recorded in the design database, a member in-range determining unit configured to determine whether coordinates of an object point selected among the measurement points recorded in the measurement database are of the shape calculation member by using the member shape information of the shape calculation member, and an allocated measurement data creating unit configured to record the object point in association with member identification information of the shape calculation member in the measurement database.

Data management system and management method

Provided is a work management system enabling real-time inspection by simultaneously performing work and measurements. The work management system includes a tool including a communication unit and a trigger switch, a camera unit including a communication unit, a camera capable of identifying 3D camera coordinates from an image, a posture detecting device configured to acquire camera posture information, a control unit, and a prism, and a surveying instrument including a communication unit, a tracking unit, a distance-measuring unit, an angle-measuring unit, and a control unit, wherein upon detection that the trigger switch has been used, the camera unit collects camera posture information by the posture detecting device, a tool image by the camera, position coordinates of the prism measured by the surveying instrument, and orientation information of the camera unit viewed from the surveying instrument, and obtains and stores position coordinates of a tip end position of the tool.

Work management system and work management method

A management system of the present invention includes a design database storing member identification information, member coordinates, and member shapes of construction members constituting a construction object, a management member selecting unit configured to select a management member to be managed among the construction members stored in the design database, a related member selecting unit configured to select a related member adjacent to the management member from the design database, a boundary information creating unit configured to select an adjacent portion between the management member and the related member, and with respect to the adjacent portion, as boundary information, associate identification information, adjacent portion coordinates, an adjacent portion shape of the adjacent portion, member identification information of the management member, and member identification information of the related member with each other, and a comparison result database configured to store information associated by the boundary information creating unit.

Data management system, management method, and storage medium

Provided is a novel bag-in-box having a small load on the environment. A bag-in-box includes a box body including a corrugated cardboard as a forming material, and a flexible inner bag that is accommodated in the interior of the box body, in which the inner bag is formed of a material containing a biomass-derived polyolefin resin.

Bag-in-box

A pull-up circuit prevents generation of a leak current if a difference of potentials occurs between a power source voltage of a pull-up circuit (a bus-hold circuit) and an input terminal. A control terminal is provided in the bus-hold circuit. Inputs of the input terminal and the control terminal are input to a NOR gate, and an output of the NOR gate is input to a gate terminal of a first MOSFET that controls coupling between an input terminal and the power source voltage of the bus-hold circuit. A second MOSFET ('control' MOSFET) is provided as a switch that operates by an inverted output of the control terminal. By coupling the first MOSFET and the control MOSFET in series, the coupling between the input terminal and the power source voltage is controlled with a higher precision, thereby preventing generation of a leak current.

Semiconductor device and method of controlling the same

A power source noise of a semiconductor device having a core cell configuring a logic circuit is reduced. Above the core cell configuring the logic circuit provided on a main surface of a semiconductor substrate are provided a first branch line for a first power source of the core cell, which is electrically connected to a first power source trunk line, and a second branch line for a second power source of the core cell, which is electrically connected to a second power source trunk line. The first and second branch lines are oppositely provided, thereby forming a capacitor between the first and second power sources.

Semiconductor device and storage medium

The present invention provides a semiconductor integrated circuit device having an SRAM in which leak current is reduced. In an SRAM comprising a plurality of memory cells each constructed by a storage in which input and output terminals of two inverter circuits are cross-connected and a selection MOSFET provided between the storage and complementary bit lines and whose gate is connected to a word line, a substrate bias switching circuit is provided. In normal operation, the substrate bias switching circuit supplies a power source voltage to an N-type well in which a P-channel MOSFET of a memory cell is formed and supplies a ground potential of the circuit to a P-type well in which an N-channel MOSFET is formed. In the standby state, the substrate bias switching circuit supplies a predetermined voltage which is lower than the power source voltage and by which a PN junction between the N-type well and the source of the P-channel MOSFET is not forward biased to the N-type well, and supplies a predetermined voltage which is higher than the ground potential and by which a PN junction between the P-type well and the source of the N-channel MOSFET is not forward biased to the P-type well.

Semiconductor integrated circuit device

There are provided a plurality of bridge circuits which convert the test data information from a common test bus connected to a plurality of memories of different access data widths and address decode logics to the inherent access data widths of each memory and also convert the test address information from the common test bus to the inherent bit format of each memory to supply the result to the corresponding memory. The test address information is supplied in parallel from the common test bus to a plurality of memories to realize the parallel tests. Accordingly, the test data information can be supplied in parallel to a plurality of memories of different data widths and the address scan direction in the respective memories for the test address information can be uniformed to the particular direction depending on the inherent bit format. Thereby, the memory test efficiency by the match pattern for a plurality of on-chip memories can be improved.

Semiconductor integrated circuit and testing method thereof

A semiconductor integrated circuit has a memory which can enter active state or standby state, and the memory has voltage generation circuits for bit lines and source lines with which memory cells are connected. The voltage generation circuits make the potential of the bit lines and the potential of the source lines equal to each other in response to an instruction to transition from active state to standby state. The voltage generation circuits produce a potential difference between the bit lines and the source lines in response to an instruction to transition from standby state to active state. In standby state, the potential of the bit lines and that of the source lines are equal to each other. Therefore, sub-threshold leakage does not occur between the source and drain of each memory cell. In active state, the source line potential is not varied.

Semiconductor integrated circuit and IC card

Wirings connected to a gate electrode of a slave switch circuit cell for substrate bias circuits are respectively electrically connected to a wiring for a power supply potential and a wiring for a reference potential. Thus, the switch operation of the slave switch circuit cell is made invalid. Wirings connected to n wells of respective circuit cells are electrically connected to a wiring for the power supply potential, and wirings connected to p wells of the respective circuit cells are electrically connected to the wiring. Thus, the n wells are fixed to the power supply potential, and the p wells are fixed to the reference potential.

Method of manufacturing a semiconductor device

Growing community of inventors

Kawasaki, Japan

Toshio Yamada