Nippon Steel Corporation

Toshio Wada

Shoichi Iwasa

Kenji Anzai

Yasuo Sato

Yuichi Egawa

Kikuzo Sawada

Yugo Tomioka

Hiroyuki Inoue

Yoshikazu Sugawara

Kouhei Eguchi

An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Electrically alterable n-bit per cell non-volatile memory with reference

A semiconductor memory device includes a dielectric layer formed on a conductive thin film layer constituting a shield electrode for effecting element separation in a field area, the dielectric layer connected to a dielectric layer of a capacitor with a lower electrode having part thereof opposite to part of the shield electrode through the dielectric layer, and has an increase in electrode area of a memory cell to be able to attain the high level of integration.

Semiconductor memory device having memory cells with enhanced capacitor

A method of writing or reading at least three different data in each memory cell, in a non-volatile semiconductor memory device having a plurality of memory cells, each memory cell having floating gate for setting a given threshold voltage in the memory cell. In addition, a non-volatile semiconductor memory device capable of checking if the data stored in the selected memory cell is correct by using one of at least two binary bits of the data as a parity bit, and a method of writing or reading data in or from that memory device.

Non-volatile semiconductor memory device having memory cells, each for

A MOS semiconductor device and a method of making the same are arranged to include a semiconductor substrate of a first conductivity type; a pair of impurity diffused layers of a second conductivity type different from the first conductivity type formed in the semiconductor substrate and mutually separated by a distance of 0.1 .mu.m or less; a gate insulating film including at least two layers of a silicon oxide film and a silicon nitride film and formed on a portion of the semiconductor substrate disposed between the pair of impurity diffused layers; and a gate electrode formed on the gate insulating film, wherein preferably the silicon nitride film has a thickness of 4.5 nm to 14.86 nm.

MOS-type semiconductor device and method of making the same

A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

Non-volatile semiconductor memory cell capable of storing more than two

A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region. Each reference cell has the same electrical characteristic as the memory cell, with the method including:

Method of writing into non-volatile semiconductor memory

An electrically erasable non-volatile semiconductor memory device comprising a plurality of row lines and column lines, a plurality of memory cells connected in a matrix to the plurality of row lines and column lines, a selection circuit for selecting a desired one of the plurality of memory cells, and write-control circuit for writing data into the plurality of memory cells. The write-control circuit is adapted to preset at least four voltage signals having different voltage values, and to select one of four voltage signals according to a data signal externally applied thereto and applying the selected voltage signal to the selected memory cell. Also included is read-control circuit for reading out data written into the selected memory cell and converting the data read-out from the selected memory cell into a data signal corresponding to one of the four voltage signals.

Non-volatile semiconductor memory device capable of storing multi-value

A MOS semiconductor memory device comprises a semiconductor substrate of a first conductive type; impurity diffused regions of a second conductive type different from the first conductive type formed into a plurality of spaced columns extending in a first direction on one surface of the semiconductor substrate and having functions of bit lines; a plurality of columns of element isolation insulating films formed on the impurity diffused regions of the second conductive type, with active regions formed therebetween; a plurality of MOS transistors formed in the active regions aligned in each of a plurality of rows extending in a second direction substantially perpendicular to the first direction, each MOS transistor including a gate formed on a part of the active region with a gate insulating film therebetween and source and drain formed in the impurity diffused regions of the second conductive type; and word lines each connected electrically to the gates of the MOS transistors aligned in each of the rows and extending in the second direction; wherein, when it is assumed that the plurality of columns are named as first and second columns alternately, the sources of the MOS transistors in adjacent two columns at both sides of the bit line of the first column are all connected to the bit line of the first column, and the drains of the MOS transistors in adjacent two columns at both sides of the bit line of the second column are all connected to the bit line of the second column.

MOS semiconductor memory device

Disclosed are a projection exposure method which comprises the steps of projecting patterns of first and second photo mask elements by a light including a coherent component, each photo mask element having a pattern of a single-layer structure of one of the phase shift film and the light shielding film on a substrate disposed at a predetermined position such that an optically synthesized pattern of the two patterns is formed on the substrate, and controlling a phase of at least one of a first light portion which projects the pattern of the first photo mask element on the substrate and a second light portion which projects the pattern of the second photo mask element on the substrate, such that said first and second light portions have a predetermined phase difference therebetween and a projection exposure apparatus for carrying out the abovementioned method.

Method and apparatus for projection exposure

A semiconductor memory device to be used as a mask ROM having: a MOS transistor array having MOS transistors disposed in a matrix of rows and columns, the drain-source circuits of the MOS transistors in each row being serially connected; a row selecting decoder for selecting one of the rows; first and second column lines alternately disposed in the row direction, each first column line being connected to one end of the drain-source circuit of each of the MOS transistors disposed in one column, and each second column line being connected to the other end of the drain-source circuit of each of the MOS transistors disposed in the one column; a data reading circuit for reading data stored in the MOS transistor array; a first switching circuit for selectively connecting one of the first column lines to the data reading circuit; a second switching circuit for selectively connecting one of the second column lines to a ground potential; and a column selecting circuit for selecting one of the columns of the MOS transistors, the column selecting circuit including a plurality of column select lines provided to the MOS transistor columns, respectively, wherein when one of the column select lines is activated, the first and second switching circuits connected to the first and second column lines connected to the MOS transistors in the corresponding column are made conductive at the same time.

MOS memory device

A mask ROM of the invention comprises: a plurality of memory cells arranged m a matrix; a plurality of word lines, each connecting gates of the memory cells in the lateral direction; a plurality of bit lines which are constructed by serially connecting MOS transistors constructing the memory cells; a row decoder connected to the word lines; and a column decoder connected to the bit lines in which each memory cell is constructed by an MOS transistor and a resistor connected in parallel between the source and drain of each MOS transistor. The content of each memory cell is determined by whether the resistor 8 is cut out or not so that the steps up to the cutting step of the resistors 8 can be standardized while maintaining a high density in integration of the memory cells and the turn-around time can be reduced.

Growing community of inventors

Sagamihara, Japan

Toshio Wada