Mitsubishi Denki Kabushiki Kaisha

Nippon Telegraph and Telephone Corporation

Toshio Tokita

Mitsuru Matsui

Shiho Moriai

Junko Nakajima

Masayuki Kanda

Kazumaro Aoki

Hideo Yoshida

Yasuyuki Sakai

Toru Sorimachi

It is desired to share one circuit by an encryption unitand a decryption unit. A normal data transformation unit (FL)and an inverse data transformation unit (FL)are located at point symmetry on a non-linear data transformation unit, and a normal data transformation unit (FL)and an inverse data transformation unit (FL)are located at point symmetry on the non-linear data transformation unit. Therefore, the encryption unitand the decryption unitcan be configured using the same circuits.

Block encryption device using auxiliary conversion

Block cipher apparatus using auxiliary transformation

Block cipher using auxiliary transformation

To encrypt another piece of data during encrypting process of a certain piece of data, a memoryis provided in parallel with a feedback linewhich feeds back data from an encrypting moduleusing an encryption key K to a selectorWhen an interrupt IT for processing plaintext block data Nis generated while plaintext block data Mis processed, ciphertext block data Cat timing of generation of the interrupt IT is made to be stored in a registerThe ciphertext block data Cstored in the memoryis made to be selected by the selectorat timing of completion of processing the plaintext block data N, and processing the plaintext block data Mis started.

Method and apparatus for encryption, method and apparatus for decryption, and computer-readable medium storing program

In a data transformation apparatus for transforming two arbitrary pieces of data of A input data and B input data, a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. The above configurations is connected in a cascade and the last A intermediate data and B intermediate data are output as transformation result.

Data transformation apparatus and data transformation method

The present invention can be applied to a cipher processing apparatus, which includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included. According to the invention, the cipher processing apparatus is configured by registers through for temporarily holding data, selectors A through C, through and a function f operating circuit for transforming data. An output data from the function f operating circuit is held in the register C and the selector C selects either to repeat the data transformation by the function operating circuit or not. When a cipher processing apparatus includes a function F having a configuration of repeating process and inside of the function F, a function f having a configuration of repeating process is included, the cipher processing apparatus can be embodied efficiently, which enables to reduce the circuit scale and to save electric power.

Cipher processor, IC card and cipher processing method

Data transformation apparatuses and methods for transforming two arbitrary pieces of data of A input data and B input data, wherein a first nonlinear transformation of the A input data is performed using a first key parameter, a transformed result is output, an XOR operation of the transformed result and the B input data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. On the other hand, the B input data is input to a next sub-transformation unit as A input data. A second nonlinear transformation of the B input data is performed using a second key parameter, the transformed result is output, an XOR operation of the transformed result and the B intermediate data is performed to output an XORed result as B intermediate data, and the B intermediate data is input to a next sub-transformation unit as B input data. The above configurations are connected in a cascade and the last A intermediate data and B intermediate data are output as a transformation result.

The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift register to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.

Error-correcting encoder, error-correcting decoder and data transmitting

The present invention provides an error-correcting encoder and an error-correcting decoder which encode/decode a plurality of information symbols in parallel with a reduced number of shifts, which enables a reduction in the processing time. The error-correcting encoder of the invention includes a shift-register including stages equal to a predetermined number of check symbols for inputting different information symbols in parallel from a plurality of input terminals. The encoder also includes a Galois field multiplier for multiplying each coefficient and a Galois field adder to obtain the predetermined number of check symbols from the information symbols. The encoder can generate the predetermined number of check symbols with shifts, the number of which is reduced according to the number of parallel inputs. The syndrome generator of the error-correcting decoder of the invention includes a plurality of Galois field multipliers which multiply the coefficients for calculating syndromes for inputting different code symbols in parallel from a plurality of input terminals. The syndrome generator also includes a Galois field adder and a shift-register(s) to obtain the predetermined syndrome generating polynomial. The syndrome generator can obtain the desired syndromes with shifts, the number of which is reduced according to the number of parallel inputs.

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Tokyo, Japan

Toshio Tokita