Nec Corporation

Eisai Company, Limited

Toshio Takeshima

Hiroshi Sugawara

Masakatsu Takanashi

Masako Tajima

Yukihisa Miyazawa

Kota Okinaga

Naoaki Sudo

Masayoshi Ohkawa

Tadahiko Sugibayashi

Isao Naritake

Mitsutaka Morimoto

Noaki Sudo

Yuji Okuto

An EBV strain infecting epithelial cells and a stomach cancer cell line cancerated by EBV are established to clarify the mechanism of canceration of epithelial cells into stomach cancer by EBV and to develop a chemotherapeutic agent for stomach cancer cancerated by EBV. Further, a stomach cancer cell line stably producing EBV-related antigens is established to develop a diagnostic drug for stomach cancer cancerated by EBV. According to the present invention, GTC-4 cell line was established through culture of stomach cancer tissues. GTC-4 produced the EBV strain infecting epithelial cells and simultaneously produced EBV-related antigens stably in the supernatant.

EBV-infected stomach cancer cell line

A level detector enables high speed operation at low voltage with eliminating dependency to fluctuation of a power source voltage and tolerance in a device, and further permits stable operation. The level detecting circuit performs predetermined level shifting of a voltage level of an input signal input from a load voltage generating circuit, with a resistance type potential division by a voltage dividing resistor element using a reference power source voltage independent of a power source voltage to be supplied to own circuit. In this case, a differential amplifier feeds an output depending upon a difference between a level shifted signal from the level shifter and a predetermined reference voltage for leading an output thereof as a detection output. Also, since the reference power source independent of the power source voltage is used, influence of fluctuation of the power source voltage for the circuit is restricted to realize stable operation.

Negative voltage level detection circuit

In order to reduce the number of erase operations of a nonvolatile memory cell which stores a threshold voltage selected from among a plurality of threshold levels, a plurality of programming operations are implemented before an erase operation. That is, the programming operations are executed which respectively vary the threshold voltage of the memory cell to a different one of the plurality of threshold levels, or retain the previously stored threshold voltage of the memory cell. Thereafter, the memory cell is erased so as to return the voltage which is stored in the memory cell to a predetermined level, in response to all of the threshold levels having been used in the programming operations.

Method of programming a multilevel nonvolatile memory cell with reduced

The present invention relates to a booster circuit which uses multiple pump circuits to provide high voltages. The pump circuits are provided with an input voltage Vcc and are generally each made up of a diode and a capacitor. A node driving circuit provides driving signals to driving nodes and thereby to the pump circuits. The driving nodes are connected by a charge transfer switch which is selectively activated so as to allow charge that would otherwise be lost to ground to be conserved for inclusion in the final high-output voltage.

Booster circuit

Disclosed is a method of restoring data in a non-volatile semiconductor memory which has a memory cell array that a plurality of electrically programmable memory cells to be set of several threshold voltages are matrix-disposed, a data erasing means that divides the memory cell array into several blocks and erases in the lump data stored in memory cells included in the divided block, a data writing means that writes data into the memory cells, a data reading means that reads out data from the memory cells, and a control means that controls the operations of the data erasing means, data writing means and data reading means, wherein the non-volatile semiconductor memory has a function that detects the deterioration of data stored in the memory cells and then restores it, the method having the steps of: detecting the data-deterioration state of memory cells included in the block; conducting a light erasing operation with a threshold voltage change smaller than that of an ordinary erasing operation to an erase block including a memory cell with a data-deterioration state that cannot be restored by additional writing; then detecting the data-deterioration state of the memory cells again; and restoring data of a memory cell that a data deterioration is detected.

Method of restoring data in non-volatile semiconductor memory

The non-volatile semiconductor memory of the present invention comprises a memory cell transistor to which three or more threshold values are set by controlling the floating gate-source voltage, wherein the voltage of the floating gate is maintained constant while the voltage applied to the source is varied.

Non-volatile semiconductor memory device having a memory cell capable of

A variation in threshold of a memory cell is detected at a higher speed. A multi-valued nonvolatile semiconductor memory has a nonvolatile memory cell 41 for storing n-values (n.gtoreq.3) of data as thresholds in one cell, a reference signal generator 44 for emitting a reference signal group Vri (i.ltoreq.(n-1)), a reference signal group VriH(=Vri+.DELTA.V) and a reference signal group VriL(=Vri-.DELTA.V), a differential amplifier 43 for receiving either one of signals Vci (Vci&lt;VriL&lt;Vri&lt;VriH&lt;Vc(i+1)) corresponding to the stored data in the memory cell 41 at one input terminal and receiving the reference signal groups Vri, VriH or VriL at the other input terminal, a latch circuit 46 for latching output of the differential amplifier 43, a comparator 47 for comparing the output of the differential amplifier 43 with the output of the latch circuit 46, and a controller 48 for emitting control signals D1 to D6 in accordance with the output of the latch circuit 46 and controlling the differential amplifier 43 and the comparator 47.

Nonvolatile semiconductor memory having memory cells each storing

In order to provide a voltage booster circuit to be controlled for generating either of a positive high voltage and a negative high voltage for economizing chip size, a voltage booster circuit of the invention, having a charge transfer circuit wherein charges are transfered from a lowest node (N10) to a highest node (N15), comprises switching means (1 and 2) for selecting one of a positive high voltage output mode and a negative high voltage output mode. A positive high voltage (VPP) is output from the highest node (N15) by supplying a power supply voltage (VCC) to the lowest node (N10) in the positive high voltage output mode, and a negative high voltage (VBB) is output from the lowest node (N10) by grounding the highest node (N15) in the negative high voltage output mode.

Voltage booster circuit

A non-volatile semiconductor memory configured to be able to write a multi-value information into a memory cell, comprises a memory cell array composed of a number of memory cell transistors. First and second write circuits receive first and second quaternary input data, and generate first and second writing bit line voltages having a level corresponding to the value of the first and second quaternary input data, respectively. A column selection circuit selects first and second bit lines from a number of bit lines of the memory cell array, in accordance with a row address signal, and for simultaneously supplies the first and second writing bit line voltages to the selected first and second bit lines, respectively, at the time of the writing. Thus, two items of quaternary data can be simultaneously written into two memory cell transistors included in memory cell transistors of one row selected by one word line.

Non-volatile semiconductor memory capable of writing multi-value

On programming a selected memory cell of a nonvolatile semiconductor memory, first programming (S11) of the selected memory cell is made by applying a first programming pulse to the selected memory cell to make the selected memory cell have a programmed threshold voltage (Vtm). First verification (S12) is made whether the selected memory cell has the programmed threshold voltage which is not greater than a first predetermined upper limit voltage (Vt1). When the selected memory cell has the programmed threshold voltage greater than the Vt1, the first programming is again made. When the selected memory cell has the programmed threshold voltage not greater than the Vt1, second verification (S13) is made whether the selected memory cell has the programmed threshold voltage which is not greater than a second predetermined upper limit voltage (Vt10) less than the Vt1. When the selected memory cell has the programmed threshold voltage greater than the Vt10, second programming (S13) of the selected memory cell by applying a second programming pulse different from the first programming pulse to the selected memory cell so as to make the selected memory cell have the programmed threshold voltage which is not greater than the Vt10. When the selected memory cell has the programmed threshold voltage not greater than the Vt10, programming of the selected memory cell is completed.

Programming which can make threshold voltages of programmed memory cells

In a nonvolatile semiconductor memory, in addition to a first voltage generating circuit for supplying various voltages to memory cell transistors in various operations, there is provided a second voltage generating circuit for supplying various voltages to a dummy cell in a reference voltage generating circuit in the various operations. The second voltage generating circuit is configured to supply a dummy cell writing voltage to the dummy cell, one time only when the erase operation for the memory cell transistors has been carried out. Accordingly, with a very simple construction, the progress of the deterioration of the dummy cell and the memory cell transistor can be made close to each other, so that the working life of the nonvolatile semiconductor memory can be lengthened.

Nonvolatile semiconductor memory having an improved reference voltage

A semiconductor random access memory device is subjected to a parallel testing operation to see whether or not a defective memory cell is incorporated in the semiconductor random access memory device; in the parallel testing operation, a test bit of logic '1' level is sequentially written into a first predetermined address of each of data storage blocks by changing a column address, then, a test bit of logic '0' level is written into a second predetermined address of each of the data storage blocks by changing the column address again, and the write-in operation is repeated so as to form a checker-like bit pattern in each data storage block; after the formation of the test pattern, the test bits are sequentially read out from the first predetermined address of the data storage blocks to a read and write data bus system to see whether or not any one of the test bits are inconsistent with the other test bits so that the parallel testing is carried out on various bit patterns.

Dynamic random access memory device having a parallel testing mode for

A dynamic memory device having a plurality of one-transistor type memory cells is disclosed. The memory device has a plurality of pillar-like semiconductor protrusions. The transfer gate transistor of a memory cell is formed along the upper portion of the pillar-like semiconductor protrusion such that its channel region is positioned at a side surface of the upper portion, and the storage capacitor of the memory cell is formed along the lower portion of the pillar-like semiconductor protrusion.

Growing community of inventors

Tokyo, Japan

Toshio Takeshima