International Business Machines Corporation

Magic Technologies, Inc.

Hitachi Global Storage Technologies Netherlands B.v.

Toshio Sunaga

Hisatada Miyatake

Shinpei Watanabe

Hideo Asano

Koji Kitamura

Kohki Noda

Hiroshi Umezaki

Masaya Mori

Kohji Kitamura

Yoshihisa Takatsu

Sang Hoo Dhong

Toshiaki Kirihata

Kohji Hosokawa

Lejan Pu

Yoichi Taira

Hiroaki Suzuki

Yutaka Nakamura

Takeo Yasuda

Chao-Hung Chang

Hyun J Shin

Hiroyuki Ono

Lewis M Terman

Norio Fujita

Perng-Fei Yuh

Minoru Furuta

Hisatada Miyatke

Koji Hosokawa

Kohji Kiramura

Systems and methods to improve reliability of sensing operations of semiconductor memory arrays requiring reading references such as MRAM or any type of phase change memory (PCM), and to improve yield of the memory arrays have been achieved. The memory array is divided into multiple parts, such as sections or segments. Reference word lines or reference bit lines or both are deployed in each of the multiple parts. Thus, the distance between an accessed line and the correspondent reference line is reduced, and hence the parasitic parameter tracking capability is enhanced significantly. Additionally spare reference word lines or spare reference bit lines can be deployed in each of the multiple parts.

Replaceable, precise-tracking reference lines for memory products

Systems and methods for realizing reference currents to improve reliability of sensing operations of segmented semiconductor memory arrays have been achieved. Preferred embodiments of the invention comprise MRAM arrays but the invention could be applied to any other memories requiring access on small, segmented arrays. All embodiments of the invention comprise a folded bit lines scheme, either in adjacent bit lines or in segment-to-segment folded bit lines. In two embodiments alternate strapping of Poly-Si Word Lines in every second segment is achieved by metal layer of Read Word Line and Write Select Line. An embodiment has stored 1 and 0 cells on both sides of a selected segment to be read.

Reference cell architectures for small memory array block activation

A memory system includes: a high-voltage-supply booster circuit for driving an access control circuit from a low voltage for memory access to a high voltage for memory access by supplying electric charge that is stored in advance to an access control circuit in response to an access start request for a memory cell array; and a low-voltage-supply booster circuit for absorbing excess electric charge when the access control circuit is switched from the high voltage to the low voltage in response to an access end request for the memory cell array.

Memory system with low current consumption and method for the same

The present invention relates to a memory system including a memory cell array and being connected to an address input, a command input, and a data input/output, said memory system including latching circuits (RALTH and WALTH) for latching a read address and a write address being inputted from the address input, an address selection circuit (ACOMSEL) for selecting, as an access address, any one of the read address and the write address being latched in the latching circuits, a read latching circuit (PFLTH) for latching a read data being read from the memory cell array, a write latching circuit (DINLTH) for latching a write data being inputted from the data input/output and a control circuit (ACTL) for controlling the access address being selected by said address selection circuit in response to a command being inputted from said command input, said control circuit for controlling, if the memory cell corresponding to said selected access address is activated and further said selected access address is a write address, a timing of writing the write data being latched by said write latching circuit into the activated memory cell.

Method of controlling memory and memory system thereof

A memory including at least one memory cell array and an access control circuit for controlling access to the memory array. The access control circuit includes an access command circuit (ADRCTL) that receives a first (CE) and a second (ADV) input signals and outputs an access command signal (ACMDS) enabling commencement of memory access, and a command discriminating circuit (CMDDEC) that receives the first (CE) and second (ADV) input signals, a third (OE) and a fourth (WE) input signals, and a clock signal (CLK), and that outputs a command discriminating signal (WRITE) for specifying whether the access command signal is for a read operation or a write operation.

Memory and method of controlling access to memory

The objective of the present invention is to provide a semiconductor storage device wherein a low active current is obtained by reducing the number of sense amplifiers to be activated at a time. An SDRAM has a divided word line structure, and includes a plurality of banks, each of which includes arrays ARto ARand 4K main word lines MWL. A row address signal is fetched in response to a row address strobe signal, and a segment address signal is fetched in response to a column address strobe signal. A main row decoder MRD activates main word lines MWL, MWL, MWLand MWLin response to the row address signal, and a segment row decoder SRD selects only an array ARin response to a segment address signal, and activates only 1K sense amplifiers SA corresponding to the selected array AR. When the main word lines MWL, MWL, MWLand MWLare activated, the segment word lines in arrays ARto ARare not activated, so that data are not destroyed.

Semiconductor storage device

A non-volatile memory device according to one embodiment comprises a plurality of memory cells each comprising a magneto resistive element and a selection transistor; wherein at least some of the memory cells are arranged into a two dimensional array; a first interconnect line extending in a first direction of the memory array and functioning as a gate electrode of a selection transistor included in each memory cell; a second interconnect line extending in the first direction of the memory array; a third interconnect line extending in a second direction; wherein the magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines, wherein the second interconnect line extends at least partially along all magneto resistive elements in a particular one of the memory cells.

Non-volatile memory device

In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiOlayer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiOlayer or epitaxial growth on the SiOlayer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.

Magnetic head of magnetoresistance effect type and process for production thereof

A magnetic random access memory (MRAM) array is disclosed herein in which a plurality of wordlines and a plurality of bitlines are provided in matrix form, the wordlines including read wordlines and write wordlines, and memory elements are provided at the intersections of the wordlines and the bitlines, memory elements, respectively, including at least a ferromagnetic layer having a magnetization direction determined by the orientation of a magnetic field generated by an electric current passing through the bitline, and a read wordline driver connected to the memory array adapted to provide a first read signal to a first read wordline of a plurality of read wordlines, wherein a second read signal is provided to activate a second read wordline while the first read wordline remains activated.

MRAM array and access method thereof

Embodiments of the present invention provide method and device for searching fixed length data. The device includes a hash operation means for operating and outputting a hash value of inputted fixed length data, a data table memory consisting of N numbers of memory banks, where N is an integer that is more than and equal to 2, the data table memory for storing a data table holding a large number of fixed length data, a pointer table memory for storing a memory pointer table holding a memory address at which each fixed length datum is stored with the hash value as an index, and a comparison means for simultaneously comparing a plurality of fixed length data stored at the same memory address in the N numbers of memory banks with a single fixed length datum inputted to the hash operation means, the comparison means for outputting results of the comparison.

Method and device for searching fixed length data

A communication control apparatus includes search information associated with a tree structure. A mask prefix is associated with at least one entry, each entry including information on the mask length of a mask prefix associated therewith and a sort key. Each entry is assigned to a node in the tree structure according to a sorting order. Each node is linked to a different node at the next lower hierarchy via a branch based on the entry of the node. A destination address of the packet received is first extracted, and a search target node specified by a search control for an entry having information on the best matched prefix of the extracted address is then searched for. After completion of the node-by-node search process, a transfer route is determined for the packet received based on the longest prefix amongst the most appropriate prefixes of all the current search target nodes.

Communication control apparatus and method for searching an internet protocol address

The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an address comparison circuit compares a predecoded signal, output by a predecoder, with the defective predecoded signals PDRA, output by the redundant predecoders. In the case of a 2-bit predecoding system, the address comparison circuit compares the predecoded signal PRA with the defective predecoded signal PDRA using four bits in order to compare the row address signal RA with the defective row address signal DRA using groups of two bits.

A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding pairs of bit lines at high speed. This is accomplished by a sense amplifier including CMOS inverters cross-connected or connected in loop, a P-channel MOS transistor for shutting the power off during standby, and N-channel MOS transistors for initializing the output of the sense amplifier during standby. A ground terminal of the inverter is connected to a bit line through a transistor of a bit switch, and a ground terminal of the inverter is connected to a bit line through a transistor of a bit switch.

Magnetic memory device

A non-volatile memory device according to one embodiment includes a plurality of memory cells each comprising a magneto resistive element and a selection transistor, where the memory cells are arranged into a two dimensional array. A first interconnect line extends in a first direction of the memory array and functions as a gate electrode of a selection transistor included in each memory cell. A second interconnect line extends in the first direction of the memory array. A third interconnect line extends in a second direction. The magneto resistive element of at least some of the memory cells is sandwiched between the second and third interconnect lines.

To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

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Ohtsu, Japan

Toshio Sunaga