Hitachi, Ltd.

Other

Elpida Memory, Inc.

Hitachi Tobu Semiconductor

Ps4 Luxco S.a.r.l.

Micron Technology Incorporated

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Longitude Semiconductor S.a.r.l.

Akita Electronics Co., Ltd.

Hitachi Ulsi Engineering Corp.

Hitachi Hokkai Semiconductor Ltd.

Epida Memory, Inc.

Toshio Sugano

Atsushi Hiraishi

Seiichiro Tsukui

Masachika Masuda

Yoshinori Matsui

Hiroaki Ikeda

Hirotaka Nishizawa

Tamaki Wada

Michiaki Sugiyama

Shunichi Saito

Yasushi Takahashi

Masayasu Kawamura

Masayuki Watanabe

Susumu Hatano

Yoshiaki Wakashima

Kensuke Tsuneda

Kunihiko Nishi

Yoji Nishio

Kiyoshi Inoue

Koichi Kimura

Atsushi Nakamura

Takashi Tsunehiro

Hideki Osaka

Aizo Kaneda

Masahiro Yamaguchi

Kazuya Ito

Akihiko Iwaya

Michio Tanimoto

Fumiyuki Osanai

Suguru Sakaguchi

Michiharu Honda

Yutaka Kagaya

Toyohiko Komatsu

Shigeru Suzuki

Takeshi Komaru

Tohru Yoshida

Kohji Nagaoka

Kohji Serizawa

Masashi Horiguchi

Masakazu Aoki

Kazumasa Yanagisawa

Toshio Sasaki

Kayoko Shibata

Seiji Funaba

Satoshi Isa

Tsutomu Hara

Yasuhiro Takai

Koichiro Aoki

Kazuki Sakuma

Takashi Ono

Takuo Iizuka

Masayuki Sorimachi

Atsuo Koshizuka

Hiroki Fujisawa

Asao Nishimura

Toshio Yamada

Masayuki M Nakamura

Seiji Narui

Satoshi Nakamura

Tatsuya Nagata

Masamichi Ishihara

Hidetoshi Iwai

Yasunori Yamaguchi

Toshio Miyamoto

Tomoaki Kudaishi

Hiroya Shimizu

Tomohiko Sato

Jiro Sawada

Masahiro Yamamura

Takayuki Okinaga

Tadao Kaji

Hideshi Fukumoto

Takashi Araki

Takashi Emata

Tsuyoshi Tomoyama

Noboru Shiozawa

Shinobu Takeura

Masanori Shibamoto

Norihiko Kasai

Ichirou Anjou

Wataru Kikuchi

Shuichiro Azuma

Seiichirou Tsukui

Yukio Kanezawa

Masakatsu Goto

Yoshiaki Anata

Yasushi Sekine

Tetsuji Kohara

Sadao Morita

Tomoyoshi Miura

Mutsuo Tsukuda

Kouji Nagaoka

In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Memory module and memory system

Apparatuses are presented for a semiconductor device utilizing dual I/O line pairs. The apparatus includes a first I/O line pair coupled to a first local I/O line pair. A second I/O line pair may be provided coupled to a second local I/O line pair. The apparatus may further include a first bit line including at least a first memory cell and a second memory cell, and a second bit line including at least a third memory cell and a fourth memory cell may be provided. The first local I/O line pair may be coupled to at least one of the first and second bit lines, and the second local I/O line pair is coupled to at least one of the first and second bit lines.

Apparatuses and methods for a memory device with dual common data I/O lines

A semiconductor device includes a plurality of memory cells, an access circuit configured to perform a data read operation, a data write operation and a data refresh operation on the memory cells, the access circuit to operate in a selected one of a first mode that is ready to perform and a second mode that is not ready to perform, and a judgment circuit configured to respond to first command information, to cause, when the access circuit is in the first mode, the access circuit to perform the data refresh operation, and to cause, when the access circuit is in the second mode, the access circuit to exit from the second mode and then to perform the refresh operation.

Semiconductor device

Disclosed herein is a device that includes a silicon interposer having wiring lines on first and second wiring layers. The wiring lines includes first, second and third wiring lines provided on the first wiring layer and a fourth wiring line provided on the second wiring layer. The third wiring line is arranged between the first and second wiring lines on the first wiring layer. The fourth wiring line is overlapped with the third wiring line. Each of the first, second and fourth wiring lines conveys a power supply potential to first and second semiconductor chips mounted on the silicon interposer, and the third wiring line conveys a first signal communicated between the first and second semiconductor chips.

Semiconductor device having silicon interposer on which semiconductor chip is mounted

Disclosed herein is a memory module that includes a module substrate, data connectors, memory devices, and data register buffers. A first main surface of the module substrate has first and second memory mounting areas. One of the first and second main surfaces of the module substrate has a register mounting area located between the first and second memory mounting areas in a planner view. The memory devices include a plurality of first memory devices that are mounted on the first memory mounting area and a plurality of second memory devices that are mounted on the second memory mounting area. The data register buffers are mounted on the register mounting area. The data register buffers transfers write data supplied from the data connectors to the memory devices, and transfers read data supplied from the memory devices to the data connectors.

Memory module including plural memory devices and data register buffer

Disclosed herein is a device that includes: a data strobe terminal; a data terminal; a first output driver coupled to the data strobe terminal; a second output driver coupled to the data terminal; and a data control circuit configured to enable the first and second output drivers to function as termination resistors in different timings from each other.

Semiconductor device having ODT function

An address signal line having a stub structure connects between at least three memory elements and a data transferring element and transmits address signals for the memory elements. An address terminal of the data transferring element has an impedance lower than a characteristic impedance of the address signal line. A wiring length TLfrom the data transferring element to a first branch point Swhere a branch line is branched at a shortest distance from the data transferring element is configured to become equal to or greater than a wiring length TLfrom the first branch point Sto a second branch point Swhere a second branch line is branched. A wiring length TLfrom the second branch point Sto a third branch point Swhere a third branch line is branched is configured to become greater than the wiring lengths TLand TL

Apparatus having a wiring board and memory devices

A memory module includes a plurality of memory chips, a plurality of data register buffers, and a command/address/control register buffer mounted on a module PCB. The data register buffers perform data transfers with the memory chips. The command/address/control register buffer performs buffering of a command/address/control signal and generates a control signal. The buffered command/address/control signal is supplied to the memory chips, and the control signal is supplied to the data register buffers. According to the present invention, because line lengths between the data register buffers and the memory chips are shortened, it is possible to realize a considerably high data transfer rate.

Load reduced memory module and memory system including the same

A multi-layer printed circuit board for mounting memories, includes: laminated wiring layers on which wiring is arranged; and a plurality of interlayer connection components which electrically connect at least two of the wiring layers. At least one of the plurality of interlayer connection components is a blind via-hole.

Multi-layer printed wiring board

Growing community of inventors

Tokyo, Japan

Toshio Sugano