Kabushiki Kaisha Toshiba

Aisin Aw Co., Ltd.

Toshiba Electronic Devices & Storage Corporation

Toshio Shiramatsu

Norio Nakamura

Nobuyasu Goto

Masaru Hashimoto

Katsuyuki Omi

Mitsuo Tsuzuki

Hiroyuki Sugiyama

A linear solenoid driving device that drives a linear solenoid, the linear solenoid driving device includes a driving circuit that performs switching control over a switching element connected to the linear solenoid based on a driving command; a current detection circuit that has a detection resistor which is connected to the switching element and the linear solenoid, and detects a current, and an operational amplifier which amplifies a voltage across both ends of the detection resistor and outputs the amplified voltage; a reference voltage output circuit that outputs a reference voltage which has a same temperature characteristic as an output voltage of the operational amplifier; and a control unit.

Linear solenoid driving device

The battery monitoring circuit includes a first switch element, a second switch element, a third switch element. The battery monitoring circuit includes a first output capacitor connected to the second end of the first switch element at a first end. The battery monitoring circuit includes a first output controlling switch element connected between a second end of the first output capacitor and the ground. The battery monitoring circuit includes an AD converter that analog-to-digital converts a signal responsive to a voltage at an output terminal between the second end of the first output capacitor and the first output controlling switch element. The battery monitoring circuit includes a controlling circuit that controls turning the first to third switch elements and the first output controlling switch element and controls the AD converter.

Battery monitoring circuit and battery monitoring system

A delay-time variable filter delays an input signal by a desired time according to a control signal from a control input node and outputs the delayed input signal, and a positive feedback loop circuit changes the output signal (sinusoidal wave signal) from this filter, and provides a positive feedback of the binary pulse signal to the input side of the filter at a desired level for carrying out an oscillation. This positive feedback loop circuit includes a circuit for changing the signal into a binary signal and providing a positive feedback of the binary signal to the input of the filter by limiting the signal at a desired amplitude. As the delay-time variable filter, a quartic Butterworth low-pass filter is used, for example. As the positive feedback loop circuit, there is used a voltage comparator circuit that changes an input signal into a binary signal and outputs a pulse signal of a desired amplitude.

Voltage-controlled oscillator, phase synchronization circuit and signal processing circuit

A phase-locked loop circuit and recording/reproducing apparatus of this invention include a distributor (11) for receiving reproduction data to distribute and output it as n reproduction data, a phase comparator group (6) having n phase comparators for sequentially receiving the distributed reproduction data to compare the phases of the reproduction data with that of a reproduction clock, a frequency comparator (5) for receiving a reference clock and the reproduction clock to compare their frequencies, a selector (7) for receiving a switching control signal, the phase comparison result, and the frequency comparison result, and selecting either one of the phase comparison result and the frequency comparison result to output the selected one as a voltage signal, a charge pump (8) for receiving the voltage signal and converting it into a current signal to output the current signal, a loop filter (9) for receiving the current signal to output a low-frequency voltage signal, and a VCO (10) for receiving the low-frequency voltage signal to output a reproduction clock having a corresponding frequency.

Phase-locked loop circuit having loop performing feedback control to

In this filter circuit, the emitter of a transistor Q1 is connected to the collector of a transistor Q2, and the base of the transistor Q2 is connected to the emitter of a transistor Q3 and the collector of a transistor Q4. The base of the transistor Q4 is connected to the collector of the transistor Q2. A capacitor C1 is connected between the emitters of the transistors Q2 and Q4, and a capacitor C2 is connected between the collectors of the transistors Q2 and Q4. With this arrangement, the filter circuit consumes a small power, is hardly influenced by the parasitic capacitance, can operate at high frequencies, and has a wide dynamic range.

Filter circuit capable of setting various filter characteristics

A signal processing circuit has a differential circuit for differentiating an analog signal and a comparator circuit for converting the signal output from the differential circuit into a digital signal. The signal processing circuit is characterized by further comprising a delay circuit for delaying the converted digital signal by a predetermined period of time. In the signal processing circuit of the present invention, the analog signal is first differentiated and digitized, and then, finally, delayed by the digital delay circuit. With such an arrangement, analog filters can be dispensed with, thus enabling most of the signal processing circuit to be built into the IC circuit, and to be of more simple design.

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Yokohama, Japan

Toshio Shiramatsu