Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Other

Yamanouchi Pharmaceutical Company Ltd.

Hitachi Maxell, Limited

Solid State Storage Solutions LLC

Hitachi Tohbu Semiconductor, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Vlsi Engineering Corp.

Fujizoki Pharmaceutical Co., Ltd.

Hitachi Usli Systems Co., Ltd.

Toshio Sasaki

Toshihiro Tanaka

Katsutaka Kimura

Hitoshi Kume

Masataka Kato

Tetsuo Adachi

Yoshihiko Yasu

Toshiaki Masuhara

Ryo Mori

Kazumasa Yanagisawa

Osamu Minato

Kazuki Fukuoka

Takashi Osono

Takashi Kuraishi

Shunichi Watanabe

Yoshihiko Oka

Satoru Nakanishi

Hiroshi Gushima

Takeshi Saito

Yuji Tanaka

Mariko Ohtsuka

Masashi Horiguchi

Koichiro Ishibashi

Takao Watanabe

Masakazu Aoki

Takashi Miyamoto

Hitoshi Tanaka

Yoshio Sakai

Kazushige Ayukawa

Toshio Yamada

Jun Sato

Yasuto Igarashi

Hiroshi Yamaguchi

Keisuke Murakami

Kiyoshi Inoue

Hiromichi Suzuki

Katsuhiro Shimohigashi

Masaharu Kubo

Toshio Sugano

Isao Takahashi

Osamu Ozawa

Fujio Ito

Seiichiro Tsukui

Shigeru Suzuki

Shigeru Sakairi

Mikio Matoba

Ken Sugawara

Hideo Eiki

Shigeru Honjiyo

Kiyoshi Susaki

Toshiaki Miyoshi

Shuichi Takamura

Hiroyuki Uchiyama

Yoshinobu Nakagome

Ryoichi Hori

Yasushi Takahashi

Kazuyoshi Oshima

Kazuyuki Miyazawa

Hiroaki Kotani

Hisashi Nakamura

Masamichi Ishihara

Hidetoshi Iwai

Atsushi Nozoe

Minoru Nagata

Akinobu Watanabe

Toshiyuki Sakuta

Masatoshi Ohtake

Naoki Ozawa

Katsuro Sasaki

Kazunori Furusawa

Yasuhiro Kasama

Shinichi Ikenaga

Akihisa Uchida

Hisao Katto

Eiji Miyamoto

Hidehito Obayashi

Kiyoshi Aiki

Kotaro Nishimura

Norikazu Hashimoto

Tokumasa Yasui

Hiromi Matsuura

Kazuhiro Kondo

Toshio Maeda

Nobuo Hamamoto

Yasunobu Aoki

Osamu Sakai

Shin-ichi Muramatsu

Masanori Tazunoki

Isamu Orita

Akihiro Tomozawa

Yasukuni Kawashima

Hiroshi Kishida

Tadashi Onishi

Hisashi Horikoshi

Hiroyuki Ikeda

Toshiaki Takahira

Efficient reduction in power consumption is achieved by combinational implementation of a power cutoff circuit technique using power supply switch control and a DVFS technique for low power consumption. A power supply switch section fed with power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in a DEEP-NWELL region formed over a semiconductor substrate. Another power supply switch section fed with another power supply voltage, a circuit block in which a power cutoff is performed by the power supply switch section, and a level shifter are formed in another DEEP-NWELL region formed over the semiconductor substrate. In this arrangement, there arises no possibility of short-circuiting between different power supplies via each DEEP-NWELL region formed over the semiconductor substrate.

Semiconductor integrated circuit device

The present invention is directed to perform fine low-voltage control without largely increasing the circuit layout area in a low-power consumption structure. In the case of shifting a region to a low-speed mode, a system controller outputs a request signal and an enable signal to a power switch controller and a low-power drive circuit, respectively, to turn off a power switch and to perform a control so that the voltage level of a virtual reference potential becomes about 0.2 V to about 0.3V. The region operates on voltages between a power supply voltage and a virtual reference potential, so that it is controlled in the low-speed mode.

A technology that makes it possible to reduce fluctuation in operating voltage for operating the circuits formed in the core region of a semiconductor device is provided. This semiconductor device is so arranged that the core region is divided into multiple functional blocks and power can be supplied and this power supply can be interrupted with respect to each of the divided functional blocks. The core region formed in the semiconductor chip is divided into multiple functional blocks. A power switch row in which multiple power switches are arranged is disposed in the boundaries between the divided functional blocks. These power switches have a function of controlling the supply of reference potential to each of functional blocks and the interruption of this supply. A feature of the invention is that reference pads are disposed directly above the power switch rows. This shortens the wires coupling together the reference pads and the power switches.

Semiconductor device

Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

Nonvolatile semiconductor memory

A plurality of MOS transistors each having an SOI structure includes, in mixed form, those brought into body floating and whose body voltages are fixed and variably set. When a high-speed operation is expected in a logic circuit in which operating power is relatively a low voltage and a switching operation is principally performed, body floating may be adopted. Body voltage fixing may be adopted in an analog system circuit that essentially dislikes a kink phenomenon of a current-voltage characteristic. Body bias variable control may be adopted in a logic circuit that requires the speedup of operation in an active state and needs low power consumption in a standby state. Providing in mixed form the transistors which are subjected to the body floating and the body voltage fixing and which are variably controlled in body voltage, makes it easier to adopt an accurate body bias according to a circuit function and a circuit configuration in terms of the speedup of operation and the low power consumption.

Semiconductor integrated circuit

The semiconductor integrated circuit has so-called SOI type first MOS transistors (MNtk, MPtk) and second MOS transistors (MNtn, MPtn). The first MOS transistors have a gate isolation film thicker than that the second MOS transistors have. The first and second MOS transistors constitute a power-supply-interruptible circuit () and a power-supply-uninterrupted circuit (). The power-supply-interruptible circuit has the first MOS transistors each constituting a power switch () between a source line (VDD) and a ground line (VSS), and the second MOS transistors connected in series with the power switch. A gate control signal for the first MOS transistors each constituting a power switch is made larger in amplitude than that for the second MOS transistors. This enables power-source cutoff control with a high degree of flexibility commensurate with the device isolation structure, which an SOI type semiconductor integrated circuit has originally.

The present invention can supply power for each circuit section by separating and connecting bus-bar () for each circuit section inside the semiconductor chip (), and, in addition, can increase the number of pads () for power supply or can use the lead () conventionally used for power supply for signals by further making the best of the characteristics that enable the connection to bus-bar () irrespective of the inner lead () pitch, by making the pitch of the pad () smaller than the pitch of the inner lead (), or by forming the pad () in a zigzag arrangement.

A plurality of inner leads, a plurality of outer leads formed in one with each of the inner lead, a bar lead of the square ring shape arranged inside a plurality of inner leads, a corner part lead which has been arranged between the inner leads of the end portion of the inner lead groups which adjoin among four inner lead groups corresponding to each side of the bar lead, and was connected with the bar lead, and a tape member joined to the tip part of each inner lead, a bar lead, and a corner part lead are included. Since the corner part lead is formed as an object for reinforcement of a frame body between adjoining inner lead groups, the rigidity of the lead frame can be increased.

Lead frame and method of manufacturing the lead frame

Growing community of inventors

Tokyo, Japan

Toshio Sasaki