Fujitsu Corporation

Nippon Electric Co., Ltd.

Nippon Telegraph and Telephone Public Corporation

Toshio Ohshima

Naoki Yokoyama

Hai-Zhi Song

Kenichi Imamura

Richard A Kiehl

Makoto Hiraoka

Haruo Shimoyama

Toshio Hanabata

Shinobu Nomoto

The method for forming a quantum dot according to the present invention comprises the step of forming an oxide in a dot-shape on the surface of a semiconductor substrate, the step of removing the oxide to form a concavityin the position from which the oxide has been removed, and the step of growing a semiconductor layeron the semiconductor substrate with the concavity formed in to form a quantum dotof the semiconductor layer in the concavity. The concavity is formed in the semiconductor substrate by forming the oxide dot in the surface of the semiconductor substrate and removing the oxide, whereby the concavity can be formed precisely in a prescribed position and in a prescribed size. The quantum dot is grown in such a concavity, whereby the quantum dot can have good quality and can be formed in a prescribed position and in a prescribed size.

Method for forming quantum dot, and quantum semiconductor device and method for fabricating the same

The quantum circuit device comprises: an asymmetrical coupled quantum dot of a main quantum dot and an operational quantum dot of a smaller size than the main quantum dot ; an asymmetrical coupled quantum dot of a main quantum dot arranged at a distance which does not permit to substantially tunnel from the main quantum dot , and an operation quantum dot having a smaller size than the main quantum dot and arranged at a distance which permits tunneling from the operational quantum dot ; and a laser device for applying to the asymmetrical coupled quantum dots a laser beam of a wavelength which resonates an inter-level energy the asymmetrical coupled quantum dots. In the sleep state, electron is present at the ground state of the main quantum dot, where no exchange interaction takes place, and in an operation, the electron is transited to an excited state of the operational quantum dot, whereby the operation is made by the exchange interactions between the adjacent operational quantum dots. Thus, relatively stable operations can be made.

Quantum circuit device and method for quantum operation

This invention is characterized in that a load resistor is constituted of a tunneling junction element(,), and a single-electron tunneling junction element(,) and the tunneling junction element(,) for load resistor are laminated to design a phase-locked circuit compact. Further, the load resistor(,) is comprised of a plurality of laminated tunneling junctions for load resistor so that the load resistor can have the proper resistance. A DC bias voltage is applied to the electrode(,) of the tunneling junction element for load resistor, and an AC pump voltage to one electrode(,) of the single-electron tunneling junction element. In the case of a plurality of phase-locked circuit gates, one electrodes of the single-electron tunneling junction elements are designed into a common electrode to which the AC pump voltage is applied, and the other electrodes are formed apart from one another two-dimensionally. Then, the phase-locked circuit gates can be formed compact by laminating the tunneling junction elements for load resistor on the other electrodes. To achieve the above structure, the dielectric constant of the insulator layer of the tunneling junction element for load resistor is made larger than that of the insulator layer of the single-electron tunneling junction element.

Phase-locked circuit device using a single-electron tunneling junction element and method of fabricating the same

The present invention relates to a semiconductor device in which an electric resistance in a carrier path is modulated by changing a voltage applied to the carrier path. The semiconductor device is provided with a semiconductor layer in which conductive particles are dispersed to scatter carriers, a first electrode, and a second electrode for passing the carriers through the semiconductor device in cooperation with the first electrode.

Semiconductor device

A single-electron tunneling (SET) element used as a logic or memory element includes at least one tunneling junction with a minute metal-insulator-metal sandwich structure, and a biasing power source which is connected in series to the at least one tunneling junction and whose ON/OFF operation is controlled by an external control input. SET oscillations are generated in the at least one tunneling junction and the generated oscillations are phase-locked to subharmonics of a pump signal supplied from an AC power source, to thus exhibit a plurality of stable phase states. Also, a plurality of gates, each including the SET element, are constituted in the form of a logic network to realize a predetermined logic operation in a computer. In the logic network, an input signal with a frequency half that of the pump signal is continually applied to a specified gate among the plurality of gates, while the biasing power sources of all of the gates are kept in ON state. Alternatively, when the biasing power source of the specified gate is switched ON, the biasing power sources of all of a first group of gates providing inputs to the specified gate, and the biasing power sources of all of a second group of gates providing inputs to the first group of gates, are kept in ON state.

Logic or memory element based on n-stable phase-locking of

A high-speed semiconductor device comprising emitter potential barrier layer disposed between an emitter layer and a base layer, a collector layer, and a collector potential barrier layer disposed between the base layer and the collector layer. The collector potential barrier layer has a structure having a barrier height changing from a high level to a low level along the direction from the base layer to the collector layer, whereby, even when no bias voltage is applied between the collector layer and the emitter layer, a collector current can flow through the device.

High-speed semiconductor device

A heterojunction semiconductor device utilizing a quantum-mechanical effect comprises a first compound semiconductor (e.g., AlGaAs) layer and a second compound semiconductor (e.g., GaAs) layer having an electron affinity different from that of the first semiconductor layer, and the first and second compound semiconductor layers forming a heterojunction interface therebetween, the first layer having an energy at the conduction band bottom thereof higher than that of the second layer and doped with donor impurities, wherein at least one concave or convex portion of the first semiconductor layer is formed at the heterojunction interface and both sides of the concave or convex portion serve as a potential well or potential barriers against electrons accumulated in the second semiconductor layer close to the vicinity of the heterojunction interface.

Heterojunction semiconductor device

A heterojunction bipolar transistor includes a base layer and a wide bandgap emitter layer. A portion of the base layer is exposed, a base electrode is formed thereon and the active region of the emitter-base junction is limited inside a semiconductor body. As a result, surface recombination current generation of the peripheral region of the junction is prevented and the emitter efficiency is improved.

Process for fabricating a heterojunction bipolar transistor

Heterojunction bipolar transistor and process for fabricating same

A compound semiconductor (e.g., GaAs) IC device structure includes: a compound semiconductor substrate having a semi-insulating compound surface region; an active element laminated layer formed on the surface region; an isolation region of a semi-insulating (intrinsic) compound semiconductor which is filled in a groove extending into the surface region through the laminated layer; and active elements formed in regions of the laminated layer, isolated by the filled groove.

Method for producing a semiconductor integrated circuit having an

When the collector, base and emitter layers of a heterojunction bipolar transistor or a tunneling hot electron transistor are vertically stacked, the thickness of the base layer is preferably small so as to increase the current gain or switching speed. A thin base layer, however, has a disadvantage in that a space of the base layer between the actual base region and the base electrode makes the base resistance too large, decreasing current gain or switching speed, or is fully depleted due to interface states, making the transistor inoperable. This disadvantage is eliminated by forming a base contact region by doping in a region in alignment with the edge of an electrode so as to remove said space, that is, the base contact region is in contact with the actual base region.

Process for fabricating heterojunction bipolar transistor with low base

The horizontal sync signal contained in the video signal from a video apparatus sometimes undergoes phase jump, resulting in failure of multiplexing of audio and video signals based on the horizontal sync signal. A sync signal switching circuit is adapted to produce a modified sync signal by switching the sync signal to a local sync signal upon occurrence of the phase jump, thereby assuring the multiplexing of audio and video signals.

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Kawasaki, Japan

Toshio Ohshima