Hitachi, Ltd.

Toshio Ogino

Tetsuya Nagata

Kenkichi Suzuki

Masakazu Saito

Michiko Takahashi

Masanobu Miyano

A display device includes a pixel region having a plurality of pixels and a peripheral circuit region disposed at a periphery of the pixel region for driving the pixels. The peripheral circuit region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a first kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the first kind is at least 3 &#x3bc;m. The pixel region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a second kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the second kind is at least 0.05 &#x3bc;m.

Semiconductor device including a TFT having large-grain polycrystalline active layer, LCD employing the same and method of fabricating them

A display device includes a pixel region having a plurality of pixels and a peripheral circuit region disposed at a periphery of the pixel region for driving the pixels. The peripheral circuit region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a first kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the first kind is at least 3 &mgr;m. The pixel region includes transistors fabricated from polycrystalline semiconductor and having a semiconductor crystalline grain of a second kind in a channel region thereof, wherein a grain size of the semiconductor crystalline grain of the second kind is at least 0.05 &mgr;m.

A semiconductor device has a thin film transistor including an insulating substrate, an island made of a polycrystalline semiconductor material and disposed on the insulating substrate, a conductive layer made of the polycrystalline semiconductor material and at least one of metals and metallic silicides and surrounding the island, a source region and a drain region spaced from the source region, the source region and the drain region being formed in said island, a gate electrode disposed on the island with an insulating film interposed between the island and the gate electrode, the gate facing a spacing between the source region and the drain region. The polycrystalline semiconductor material forming the island and the conductive layer are fabricated by initially annealing a first amorphous semiconductor material deposited on the insulating substrate with a crystallization-inducing layer made of the at least one of metals and metallic silicides and having a hole corresponding to the island, the crystallization-inducing layer being disposed on a surface of the amorphous semiconductor material on at least one of a substrate side thereof and a side thereof opposite from the substrate side, and then by depositing a second amorphous semiconductor material on the first amorphous semiconductor and annealing the second amorphous semiconductor material.

Growing community of inventors

Chiba, Japan

Toshio Ogino