Seikagaku Corporation

Micron Technology Incorporated

Ps4 Luxco S.a.r.l.

Toshio Ninomiya

Koji Kimata

Nobuo Sugiura

Chikara Kondo

Chiaki Dono

Taihei Shido

Seiichi Maruno

Hiromasa Noda

Koji Room 1201 Esupoa-Yashiroguchi Kimata

An apparatus includes a first external terminal, a first circuit, a signal line and a second circuit. The first external terminal receives at least one of data mask information and data bus inversion information. The first circuit performs one of an error check operation and a data bus inversion operation. The signal line is coupled between the first external terminal and the first circuit. The second circuit is coupled to the signal line and first a voltage level of the signal line at a substantially constant level responsive to a first control signal.

Apparatuses and methods for fixing a logic level of an internal signal line

A control circuit receives the mode signals supplied from a mode register and a read enable signal READ supplied from a control logic circuit, which activates enable signals ENto ENbased on the mode signals and read enable signal. For example, the read enable signal READ is activated when a read command is issued from the controller. One mode signal can indicate an operation mode in which a multi-purpose register is used, and another mode signal can indicate an operation mode in which the data bus inversion function is used. When a data masking operation is disabled and an error check operation is enabled, the mode register activates a protection signal SEL. When the data masking operation is enabled or the error check operation is disabled, the protection signal SEL is deactivated. The operation of a deserializer is controlled by clock signals and the protection signal SEL.

A device includes a decoder, a selector, and a plurality of registers. The decoder is configured to generate a plurality of test signals. The selector is coupled to the decoder. The selector is configured to sequentially select a test signal from the plurality of test signals and to sequentially output the test signal selected. The plurality of registers is coupled in series to each other. The plurality of registers includes a first stage register. The first stage register is coupled to the selector to sequentially receive the test signal from the selector.

Semiconductor device

A chondroitin polymerase having such properties that it transfers GlcUA and GalNAc alternately to a non-reduced terminal of a sugar chain from a GlcUA donor and a GalNAc donor, respectively, and the like; and a process for producing the chondroitin polymerase.

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Tokyo, Japan

Toshio Ninomiya