Sharp Kabushiki Kaisha Corporation

Honda Motor Co., Ltd.

Fuji Electric Systems Co. Ltd.

Fuji Electric Co., Ltd.

Sharp Kabushiki Kaisah

Toshio Naka

Hitoshi Sumida

Akinobu Teramoto

Ken-ichi Nonaka

Hiroaki Yamamoto

Masaru Kubo

Shinji Kamiya

Kazushi Naruse

Katsuki Tsuda

Shohhei Ohsawa

A miniaturizable, low-cost highly reliable inverter unit. A control circuit section for controlling operating timing of high breakdown voltage semiconductor elements included in an inverter circuit section and first and second drive and abnormality detection circuit sections for outputting drive signals for driving the high breakdown voltage semiconductor elements according to the operating timing and for feeding back an abnormality of the inverter circuit section to the control circuit section are formed on an SOI substrate as one integrated circuit chip. On the integrated circuit chip, circuit formation areas which differ in reference potential are separated from one another by dielectrics. A plurality of level shifters for transmitting signals exchanged between circuit formation areas separated by the dielectrics are formed.

Inverter unit, integrated circuit chip, and vehicle drive apparatus

In one embodiment of the present invention, an output control device is disclosed capable of reducing a chip size and realizing a low cost. An output control device includes a switching transistor controlling an output voltage by having an on/off time ratio controlled and a control IC controlling the on/off time ratio of the switching transistor on the basis of the output voltage controlled by the switching transistor. The switching transistor is made of a lateral power MOSFET.

Output control device, and AC/DC power source device, circuit device, LED backlight circuit device, and switching DC/DC converter device each using output control device

A transistor comprising a P-type high concentration impurity diffusion layer which can also serve as an emitter for a parasitic PNP transistor wherein a layer of crystal defect obtained by ion implantation of inert impurity atoms or a compound thereof is arranged in the P-type high concentration impurity diffusion layer thereby decreasing the current amplification rate of the parasitic transistor.

Parasitic PNP transistor with crystal defect layer in the emitter region

Growing community of inventors

Osaka, Japan

Toshio Naka