Texas Instruments Corporation

Mireplica Technology, LLC

Toshio Nagata

William M Johnson

Ashwin Sampath

Hamid Rahim Sheikh

John W Glotzbach

Yuan Li

Jeffrey L Nye

Shalini Gupta

David Harold Bartley

Murali S Chinnakonda

Ajay Jayaraj

Mitsuhiko Yagyu

Stephen Busch

Robert Jp Nychka

Ganesh Sundararajan

Methods and systems are disclosed for increased speed of processing operations on data in two-dimensional arrays, and for detecting a feature in an image. A method for detecting a feature in an image comprises storing, in a set of data memories within a parallel processing system, first image data representing pixels of a first image. The method further comprises storing, in a memory of a host processor coupled to the parallel processing system, feature kernel data representing a set of weight matrices. A method for increased speed of processing operations on data in two-dimensional arrays comprises storing, in a set of data memories within a parallel processing system, first array data representing elements of a first array. The method further comprises, for each of multiple selected elements within the first array, performing a processing operation on the selected element to produce an output element corresponding to the selected element.

Performance enhancement for two-dimensional array processor

Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system is provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured 'on the fly' to accommodate the parallelized code based on an allocation of memory and compute resources. Thus, the processing cluster and its corresponding system programming tool provide a system that can perform parallel processing from a serial program that is transparent to a user. Generally, a control node connected to the address and data leads of a host processor uses messages to control the processing of data in a processing cluster. The cluster includes nodes of parallel processors, shared function memory, a global load/store, and hardware accelerators all connected to the control node by message busses. A crossbar data interconnect routes data to the cluster circuits separate from the message busses.

Integrated circuit with control node circuitry and processing circuitry

Methods and apparatus to facilitate improve code division multiple access (CDMA) receivers are disclosed. An example method disclosed herein comprises: receiving a signal containing first portions that are based on known data and second portions that are based on unknown data; generating a training signal, from the received signal, that substantially represents one or more of the first portions; adapting filter coefficients using the training signal; and equalizing the received signal using the adapted filter coefficients.

Methods and apparatus to facilitate improved code division multiple access receivers

Methods and apparatus to perform frequency-domain equalization in high-speed downlink packet access (HSDPA) receivers for wireless channels with large delay-spreads are disclosed. An example method comprises computing a first frequency-domain equalizer (FDE) coefficient for a first set of multipaths, computing a second FDE coefficient for a second set of multipaths, computing a first equalized signal by equalizing a received code division multiple access (CDMA) signal with the first FDE coefficient, computing a second equalized signal by equalizing the received CDMA signal with the second FDE coefficient, delaying the first equalized signal by a delay difference between the first and the second sets, and combining the delayed first equalized signal and the second equalized signal.

Delayed combining of frequency-domain equalized wireless channels with large delay-spreads

Blind transport format detection with sliding window trace-back for evaluating decodings to candidate block lengths together with piecewise linear approximation of the reliability figure (logarithm of ratio of maximum survivor path metric minus minimum survivor path metric divided by 0 state path metric minus minimum survivor path metric) with a small lookup table plus simple logic.

Blind transport format detection system and method with logarithm approximation for reliability figure

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San Diego, CA, United States of America

Toshio Nagata