Azurengine Technologies Zhuhai Inc.

Azurengine Technologies, Inc.

Toshio Nagata

Yuan Li

Jianbin Zhu

Ryan Braidwood

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer and a plurality of columns of vector processing units coupled to the sequencer. The sequencer may include a scalar instruction decoder, a vector instruction decoder, and a plurality of scalar processors configured to concurrently execute one or more scalar instructions decoded by the scalar instruction decoder to generate one or more vectors of parameters. The vector instruction decoder may be configured to decode one or more vector instructions to generate a set of configurations with the one or more vectors of parameters embedded as one or more vectors of immediate values and send the configurations to a target column. Each column of vector processing units may be configured to repeatedly execute the vector operations in the configurations using one or more respective elements of one or more vectors of immediate values per repetition.

Vectorized scalar processor for executing scalar instructions in multi-threaded computing

Processors, systems and methods are provided for thread level parallel processing where threads in a warp are concurrently executed. A method may include sending thread block dimension information and addressing parameters stored in scalar registers of a sequencer by the sequencer to a memory port, generating a scalar memory address by the memory port and based on the thread block dimension information and the addressing parameters, and loading K words of data for a warp to a vector register from K consecutive memory addresses starting at the scalar memory address by a memory interface and a memory unit. The scalar memory address may point to a storage location of a piece of data for a first thread of the warp. And K may be a warp size representing a number of threads to be concurrently processed by executing a vector instruction.

Private memory mode sequential memory access in multi-threaded computing

Processors, systems and methods are provided for thread level parallel processing. A processor may include a sequencer configured to: decode instructions that include scalar instructions and vector instructions, execute decoded scalar instructions, and package decoded vector instructions as configurations. The processor may further include a plurality of columns of vector processing units coupled to the sequencer. The plurality of columns of vector processing units may include a plurality of processing elements (PEs) and each of the PEs may include a plurality of Arithmetic Logic Units (ALUs). The sequencer may be configured to send the configurations to the plurality of columns of vector processing units.

Mixed scalar and vector operations in multi-threaded computing

A processor may include a plurality of columns of vector processing units arranged in a two-dimensional column array with a plurality of column stacks placed side-by-side in a first direction and each column stack having two columns stacked in a second direction. The processor may further include a memory unit divided into two portions placed on two opposite sides of the column array in the second direction. Each portion may contain two memory blocks placed side-by-side in the first direction. Each memory block may contain two cache blocks placed along a first edge abutting an adjacent memory block and a plurality banks of memory cells placed to space from the first edge in the first direction by the two cache blocks and from a second edge abutting the column array in the second direction by routing channels.

On-chip memory system for a reconfigurable parallel processor

Processors, systems and methods are provided for thread level parallel processing. A processor may include a plurality of columns of vector processing units arranged in a two-dimensional column array with a plurality of column stacks placed side-by-side in a first direction and each column stack having two columns stacked in a second direction and a temporary storage buffer. Each column may include a processing element (PE) that has a vector Arithmetic Logic Unit (ALU) to perform arithmetic operations in parallel threads. At a first end of the column array in the first direction, two columns in the column stack are coupled to the temporary storage buffer for one-way data flow. At a second end of the column array in the first direction, two columns are coupled to each other for one-way data flow. The column array and the temporary storage buffer may form a one-way circular data path.

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Lake Elsinore, CA, United States of America

Toshio Nagata