Burr-brown Corporation

Toshio Murota

Toshihiko Hamasaki

Yoshiaki Shinohara

Hitoshi Terasawa

Ei-ichi Arihara

Kyoji Matsusako

Hideki Kanayama

Masayuki Ukawa

Keiji Matsuki

Shigetoshi Nakao

A waveform shaping circuit for use in a function circuit is provided which minimizes interference with a feedback circuit of the function circuit and a load. The waveform shaping circuit disposed in the function circuit includes a voltage transfer unit and a voltage-to-current converter unit. The voltage transfer unit transfers a voltage at an output terminal of an operational amplifier to the converter unit in an electrically isolated condition. The converter unit has a predetermined threshold for the magnitude of the voltage at the output terminal. The converter unit supplies an inverting input terminal of the operational amplifier with a current having a magnitude depending on a relationship in magnitude between the voltage at the output terminal and the predetermined threshold. In one embodiment of the invention the waveform shaping circuit is used to prevent the onset of instability in a high order delta sigma modulator.

Waveform shaping circuit for function circuit and high order delta sigma

An integrated circuit resistor array suitable for use as resistors included in a high performance analog integrated circuit is provided. A plurality of resistor stripes are collectively arranged in a region on a substrate. The resistor stripes are made of the same material and designed to have the same cross-sectional area. The resistor stripes are electrically connected through first metal layer conductors. Second metal layer conductors connect the stripes to external circuits. Different resistors have matched voltage dependencies.

Integrated circuit resistor array

A digital-to-analog converter is provided which compensates for relative errors among weighting elements used for D/A conversion. The converter includes a decoder, a rotator, and a weighting section. The rotator receives decoded signals from a decoder to produce rotated output signals for activating or deactivating a plurality of weighting elements, respectively, included in the weighting section. The rotated output signals assure that the same number of weighting elements are activated in each of a plurality of sub-periods of time constituting a main period of time of the D/A conversion and that each of the plurality of weighting elements is activated the same number of times during the whole main period.

Rotation system for correction of weighting element errors in

A characteristic tone in a delta-sigma analog-to-digital converter is shifted out of an audible pass band without diminishing dynamic range or signal-to-noise ratio thereof by operating the digital-to-analog converter to measure its offset voltage. If the amplitude of the measured offset voltage exceeds a predetermined value, no dither signal is applied to the input of the delta-sigma modulator. If the measured offset voltage is less than the predetermined value, a positive DC dither voltage is added to the input voltage of the delta-sigma modulator if the measured offset voltage is positive, or is subtracted if the measured offset voltage is negative.

DC dither circuitry and method for delta-sigma modulator

Differential filters for removing both normal-mode and common-mode noises are provided. A first-order differential low pass filter is composed of a first resistor connected between a first input terminal and a first output terminal, a second resistor having the same resistance value as the first resistor and connected between a second input terminal and a second output terminal, a first capacitor connected between the first output terminal and a reference potential, a second capacitor having the same capacitance value as the first capacitor and connected between the second output terminal and the reference potential, and a third capacitor connected between the first output terminal and the second output terminal.

Differential filter circuit and integrated circuit structure therefor

An inverter device is provided which comprises an inverter including a pair of transistors, and first and second delay circuits. The first and second delay circuits are connected to respective inputs of the pair of transistors so as to cause the transistors of the pair to switch with a greater time difference, thereby reducing noise due to switching operations in the inverter.

Switching control circuitry for low noise CMOS inverter

A modified sign-magnitude DAC includes first internal DAC circuitry including a first number of bit switch circuits responsive to an input word including a sign bit and a digital data word. Each bit switch circuit is coupled to a corresponding current source transistor. Second internal DAC circuitry includes the same number of bit switch circuits responsive to the input word. Each bit switch circuit of the second internal DAC circuitry is coupled to a corresponding current source transistor. The same number of binarily weighted bit current determining resistor circuits corresponding to bits of the digital data word are connected to a reference voltage conductor. The emitter of the current source transistor of each bit switch circuit of the first internal DAC circuitry is coupled by a first gain balancing resistor to the corresponding bit current determining resistor. The emitters of the current source transistor of each bit switch circuit of the second internal DAC circuitry is connected by a second gain balancing resistor to the same corresponding bit current determining resistor. The sharing of the bit current determining resistor reduces the number required by half, and also reduces the physical size of each by half, since its resistance is halved for the same bit current magnitude.

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Kanagawa, Japan

Toshio Murota