Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toshio Mukunoki

Hiroshige Hirano

Nobuyuki Moriwaki

Tatsumi Sumi

George Nakane

Tetsuji Nakakuma

Akira Sugimoto

Takao Ozeki

A semiconductor memory device is provided which can achieve high performance, such as an improvement in reliability, an improvement in yield, and the like, without increasing the chip area. The semiconductor memory device is a non-volatile semiconductor memory device operable to program and erase data, and hold the data in the absence of a supplied voltage, comprising a memory cell including a first charge localized portion and a second charge localized portion each operable to store static charge corresponding to the data. The second charge localized portion stores static charge corresponding to static charge which should be stored in the first charge localized portion, thereby serving as a backup to the first charge localized portion.

Semiconductor memory device

A semiconductor memory device which is highly reliable, is operable at a low voltage and a high speed, and is produced at a high production yield is provided. A nonvolatile semiconductor memory device capable of reading and erasing data and holding the data even while no voltage is supplied comprises a plurality of memory cells each including a plurality of local charge portions each capable of storing a static charge corresponding to the data. Either two of the local charge portions store the charges in a complementary state.

To set a threshold of a reference cell in short time in a semiconductor memory device using a variable threshold type nonvolatile memory cell as a reference current/voltage generating unit, a memory cell which keeps an initial state during an inspection process without performing write/erase operations is provided in an area of a memory cell storing data, and Vt setting of a reference cell is performed while the verification of the reference cell is performed on the basis of the memory cell which keeps the initial state during the inspection process.

Nonvolatile semiconductor memory device, such as an EEPROM or a flash memory, with reference cells

A memory cell array includes a memory cell region composed of memory cells and a sample cell region composed of word line sample cells and bit line sample cells. The word line sample cell and the bit line sample cell are formed so that by a voltage applied to word lines and bit lines, charge transfer from the floating gate electrode occurs more easily than the memory cell.

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplier to supply charge to signal lines 21 and 22; connectors 24a and 24b connecting the charge supplier 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a connector 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

Reference potential generator and a semiconductor memory device having

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying circuit to supply charge to signal lines 21 and 22; a first connection circiut 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

A reference potential generator is constituted of two signal lines 21 and 22; a charge supplying means to supply charge to signal lines 21 and 22; a first connection circuit 24a and 24b connecting the charge supplying circuit 23 and two signal lines 21 and 22 in order to supply charge to the two signal lines; and a second connection circuit 25 connecting two signal lines 21 and 22 together by the second control signal, and two signal lines are disconnected after the potentials of the two signal lines determined by the supplied charge and each of load capacitances of signal lines are averaged. A semiconductor memory device of the invention incorporating the above reference potential generator generating an exact reference potential, is able to amplify and output the potential difference between the reference potential and the potential of data readout in the bit line, and by this, '1' or '0' of readout data can be precisely determined.

The life of a semiconductor memory device can be prolonged by using a plurality of memory cells and decreasing the stress applied to the dielectric film of the memory cells storing a data value '1.' This is achieved in the present invention by decreasing the number of rewritings required to retain stored data. Specifically, the present invention utilizes a reverse and rewrite means to reverse and rewrite data back into memory cells after being read, memory means for memorizing a signal indicating whether the currently stored data is in a reversed state, and judging means for judging whether the data should be reversely output.

Semiconductor memory device including reverse and rewrite means

A semiconductor memory device comprises a main memory cell, a redundant memory cell, a redundant address data cell comprising a non-volatile memory which electrically memorizes an address of a redundant memory cell which replaced a failed memory cell in the main memory cell, a control circuit 15 and a redundant memory cell selecting circuit 16. The redundant memory cell selecting circuit serves to hold first address data which has been read from the redundant address data cell, and to compare the first address data with second address data for a read or write operation which is input via the control circuit and thereby select the main memory cell or the redundant memory cell.

Semiconductor memory device with redundant memory cell backup

A semiconductor memory device comprising a pair of bit lines, a word line, a cell plate electrode, a memory cell connected to each of the bit lines, the word line and the cell plate electrode, and a prevention means that permits only a predetermined number of readouts of data stored in the memory cell, after which the data is destroyed and is not retrieved with subsequent readout attempts.

Growing community of inventors

Osaka, Japan

Toshio Mukunoki