Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Nitto-denko Corporation

Hitachi Chemical Company, Ltd.

Toshio Miyamoto

Asao Nishimura

Masashi Horiguchi

Masaharu Kubo

Kazuyoshi Shiba

Koki Noguchi

Syouji Syukuri

Gorou Kitsukawa

Satoshi Michishita

Kunihiro Tsubosaki

Ichiro Anjo

Yoshihide Yamaguchi

Mitsuo Usami

Kunio Miyazaki

Ryuji Watanabe

Osamu Miura

Mitsuaki Katagiri

Yuji Shirai

Yukio Ookoshi

Amane Mochizuki

Toshio Sugano

Yuichi Satsu

Takao Miwa

Shigeru Takahashi

Hiroshi Kondoh

Shunichi Numata

Koji Fujisaki

Tomio Yamada

Yoshiyuki Tsuru

Eiichi Hase

Kazumasa Igarashi

Michio Ohue

Takayoshi Ikeda

Hisae Shimanoki

Yukio Okoshi

Mikio Aizawa

Tooru Fujioka

Isao Arai

Kazumichi Sakamoto

In a semiconductor integrated circuit device, testing pads () using a conductive layer, such as relocation wiring layers () are provided just above or in the neighborhood of terminals like bonding pads () used only for probe inspection at which bump electrodes () are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Semiconductor integrated circuit device

Semiconductor integrated circuit device and manufacture thereof

Semiconductor integrated circuit device with a fuse circuit

Semiconductor integrated circuit device having particular testing pad arrangement

Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

Semiconductor device

The invention is intended to increase the density for mounting the semiconductor chips on a memory-module, to increase the capacity of the memory-module, and to realize the memory-module capable of coping with high-speed buses. The memory-module comprises a plurality of WPPs having protruded terminals as external terminals and wiring portions for expanding the pitch among the protruded terminals to be wider than the pitch among the bonding electrodes of semiconductor chips, TSOPs having semiconductor chips, outer leads as external terminals, and are mounted via the outer leads that are electrically connected to the bonding electrodes of the semiconductor chips, and a module board supporting the WPPs and the TSOPs, wherein the WPPs and the TSOPs are mounted by the simultaneous reflowing in a mixed manner on the module board.

Memory-Module with an increased density for mounting semiconductor chips

Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260&#xb0; C. in order to prevent the variance of the refresh times of memory cells.

Method of manufacturing a semiconductor integrated circuit device

A semiconductor integrated circuit device includes a semiconductor substrate, a circuit element formed on one major surface of the semiconductor substrate and constituting an integrated circuit having a plurality of functions or a plurality of characteristics, an internal connection terminal, connected to the integrated circuit, for selecting one of the plurality of functions or one of the characteristics in the integrated circuit, an insulating layer covering the internal connection terminal such that the internal connection terminal is selectively exposed, and an external connection terminal arranged on the insulating layer. One of the plurality of functions or one of the plurality of characteristics is selected by a connection state between the internal connection terminal and the external connection terminal.

Semiconductor device and manufacturing method of that

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE HAVING PLURAL SEMICONDUCTOR CHIPS, WHEREIN ELECTRODES OF THE SEMICONDUCTOR CHIPS ARE ELECTRICALLY CONNECTED TOGETHER VIA WIRING SUBSTRATES OF THE SEMICONDUCTOR CHIPS

Wafer level chip size package having rerouting layers

In a semiconductor integrated circuit device, testing pads ( ) using a conductive layer, such as relocation wiring layers ( ) are provided just above or in the neighborhood of terminals like bonding pads ( ) used only for probe inspection at which bump electrodes ( ) are not provided. Similar testing pads may be provided even with respect to terminals like bonding pads provided with bump electrodes. A probe test is executed by using these testing pads or under the combined use of under bump metallurgies antecedent to the formation of the bump electrodes together with the testing pads. According to the above, bump electrodes for pads dedicated for probe testing may not be added owing to the use of the testing pads. Further, the use of testing pads provided in the neighborhood of the terminals like the bonding pads and smaller in size than the under bump metallurgies enables a probe test to be executed after a relocation wiring process.

Semiconductor integrated circuit device having bump electrodes for signal or power only, and testing pads that are not coupled to bump electrodes

A semiconductor chip is disposed within a device hole as formed in a tape base material of a tape carrier , which chip is smaller in thickness than the tape base material , and then sealing is performed by a seal resin to permit both the principal surface and back surface of such semiconductor chip to be coated therewith. And, the position of the semiconductor chip in a direction along the thickness of the tape base is set to correspond to a stress neutral plane of the TCP as a whole.

Semiconductor device and manufacturing method thereof

Disclosed is a technique capable of enhancing the degree of freedom in the layout of a rerouting layer in a wafer level CSP in which defect repairing is performed by cutting a fuse. More specifically, after the defect repairing is performed by irradiating a laser beam to a fuse, an organic passivation layer (photo-sensitive polyimide layer) is filled in a fuse opening. Thereafter, a rerouting layer, a bump land, an uppermost wiring layer, and a solder bump are formed on the organic passivation layer. In the following steps of the defect repairing, the baking process to cure an elastomer layer and the uppermost protection layer is conducted at a temperature below 260&deg; C. in order to prevent the variance of the refresh times of memory cells.

A semiconductor chip is disposed within a device hole as formed in a tape base material of a tape carrier , which chip is smaller in thickness than the tape base material , and then sealing is performed using a seal resin to permit both the principal surface and back surface of such semiconductor chip to be coated therewith. And, the position of the semiconductor chip in a direction along the thickness of the tape base is set to correspond to a stress neutral plane of the TCP as a whole.

Growing community of inventors

Kokubunji, Japan

Toshio Miyamoto