Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kaihsa

Toshio Mimoto

Yoshiji Ota

Makoto Ihara

Keizo Sakiyama

Narakazu Shimomura

Ryoichi Sato

Koichi Kamiyama

In one embodiment of the present invention, an electrostatic discharge withstand voltage evaluating device includes: an application device, including a first connecting section and a second connecting section, for supplying pulse electric charge, the first connecting section being connectable to one or whole terminal (s) of one of input terminals and output terminals of a source driver, and supplying electric charge to the source driver, the second connecting section being connectable to one or whole terminal(s) of the other one of the input terminals and the output terminals, and enabling said one or whole terminal(s) of the other one of the input terminals and the output terminals to be grounded; and a common connecting section being connectable to the plurality of output terminals of the source driver, and causing the plurality of output terminals to be electrically connected to each other, wherein the output terminals of the source driver are connected, via the common connecting section, to one of the first connecting section and the second connecting section. Therefore, the electrostatic discharge withstand voltage evaluating device can more successfully recreate how a failure occurs in a semiconductor device and can evaluate an electrostatic discharge breakdown withstand of the semiconductor device.

Electrostatic discharge withstand voltage evaluating device and electrostatic discharge withstand voltage evaluating method

A semiconductor memory device including a write protect information element for storing write permit information or write protect information for a word line or a bit line, and a write protect detection element for outputting a write permit or protect signal to a write circuit in accordance with the information stored in the write protect information element for the word line or bit line selected by a row decoder or a column decoder. When the write circuit receives a write protect signal output from the write protect detection means in the case that the write protect information means stores write protect information, the write circuit does not output a data signal.

Semiconductor memory device

A semiconductor apparatus includes multiple protection devices to protect against electrostatic discharge to an internal circuit contained in the semiconductor apparatus. The semiconductor apparatus includes plural terminals including a ground terminal, a substrate bias terminal, a power supply terminal, and an input/output signal terminal. Plural protection devices are connected between various ones of these terminals to provide the necessary discharge protection for a variety of discharge scenarios.

Semiconductor apparatus including a protection circuit against

A dynamic semiconductor memory includes a pair of complementary bit lines with a significant difference in load capacitance, storage capacitors and a pair of transistors for specifying one of the storage capacitors. One end of each storage capacitor is connected to one of the bit lines through one of the transistors and the other end is connected to the other bit line through the other transistor.

Dynamic semiconductor memories

A semiconductor integrated circuit device has an internal circuit formed on a semiconductor substrate and a first conductive layer connected to an electrode pad for communicating signals with the internal circuit. This first conductive layer may cross another signal line above or below but the insulative film which separates them includes a conductive layer in electrically floating condition such that the insulative film is protected against externally applied electrostatic noise on the electrode pad.

Semiconductor integrated circuit device with improved resistance against

A dynamic semiconductor memory comprises complementary bit lines for input and output of information, storage capacitors for storing information, and devices for specifying selected storage capacitors, each of the storage capacitors having one end connected to one end of the complementary bit lines and the other end to the other end of the complementary bit lines through one of the specifying devices to form a memory cell structure.

Dynamic semiconductor memory with smaller memory cells

In MOS ICs, particularly dynamic memory elements and the like which have a boosted signal, a pull-up circuit in the MOS IC is provided to statically hold the boosted signal output to the desired potential when power is turned on and during the active state.

MOS IC pull-up circuit

A dynamic semiconductor memory comprising memory cells each including a pair of complementary bit lines, a storage capacitor and a device for selecting that capacitor. The memory further comprises a sense amplifier and a control device, and a greater differential voltage can be obtained from these bit lines by varying the ratio of their floating capacitance. Thus, the conventional requirement for balancing the complementary bit lines is eliminated and the lines can be formed in a multi-layer structure. This contributes significantly to making the memory cell areas smaller.

Dynamic semiconductor memory with improved sense signal

An integrated circuit includes a plurality of threshold-value compensatory programmable elements integrally incorporated into a semiconductor integrated circuit, wherein, during the inspection process after assembly, the programmable elements store stationary data related to varied threshold voltages occurred during assembly process so that the varied substrate bias voltages can be restored to an ideal level by applying compensations as required. This circuit is extremely advantageous in that it effectively compensates for even the slightest variation of the threshold voltage in the integrated circuit using its extremely simplified circuit configuration, and in light of the conventional tendency in which redundant circuits containing a variety of chip parts each having a substantial area are used, against the needs for high-density part installation, the circuit embodied by the present invention effectively and securely provides means for realizing higher yield of monolithic semiconductor integrated circuits.

Monolithic semiconductor integrated circuit with programmable elements

A timing circuit with a high-voltage output has a one-stage structure and is designed to immediately start charging a booster capacitor with large capacitance so that its charging is completed within the precharge period and its charges are ready to be used in the subsequent active period. This reduces the delay time and the number of circuit elements. Thus, the circuits of this invention are adapted for large scale integration and may be combined to form a data output circuit.

LSI high-voltage timing circuit for MOS dynamic memory element

A decoder circuit for MOS memory of a redundant structure having shorter delays in access time contains a programmable element in a redundant circuit rather than connected in series on the word line driving signal.

Decoder circuit for MOS memory of a redundant structure

An input circuit of MOS integrated circuit elements for a signal transmitting circuit having a first enhancement-mode MOS field-effect transistor, the gate thereof being connected to a power source and the drain thereof being connected to a first action signal, a second enhancement-mode MOS field-effect transistor, the drain thereof being connected to said power source, and a depletion-mode MOS field-effect transistor, the gate and source thereof being connected to each other, the source of said first enhancement-mode MOS field-effect transistor being connected to the gate of said second enhancement-mode MOS field-effect transistor, the source of said second enhancement-mode MOS field-effect transistor being connected to the drain of said depletion-mode MOS field-effect transistor, the source of the depletion-mode MOS field-effect transistor being connected to the signal transmitting circuit and a boost capacitor being connected between the gate of said second enhancement-mode MOS field-effect transistor and a second action signal to result in a potential at approximately the level of the power source at a node between the second enhancement-mode MOS field-effect transistor and the depletion-mode MOS field-effect transistor.

Input circuit of MOS-type integrated circuit elements

Semiconductor circuit of MOS transistors for generation of the desired reference voltage over a wide range with almost no dependence on the power voltage. An enhancement type MOS transistor and 1st depression type MOS transistor are connected in series across the power voltage, and a 2nd depression type MOS transistor and resistance component connected are in series across the power voltage. The above 1st depression type MOS transistor is connected to the gate of the 2nd depression type MOS transistor, and the reference voltage is derived from the connection point of the 2nd depression type MOS transistor and the resistance component.

Growing community of inventors

Nara, Japan

Toshio Mimoto