Fujitsu Corporation

Matsumoto, Toshio

Toshio Matsumoto

Motokazu Kato

Kiyosumi Sato

Yoshihiro Mizushima

Katsumi Ohnishi

Hiroshi Noda

A performance adjustment apparatus connected to an information processing apparatus includes a performance adjustment unit that controls operation processing performance of an operation processing apparatus of the information processing apparatus based on a specified performance adjustment value, a performance type list information management unit that manages performance type list information comprising a plurality of pairs of a performance type and a performance adjustment value, a performance type specification unit that specifies a performance type in the performance type list information managed by the performance type list information management unit and changes the performance type, a performance adjustment value setting unit that obtains a performance adjustment value corresponding to the performance type specified by the performance type specification unit from the performance type list information management unit, and sets the obtained performance adjustment value in the performance adjustment unit.

Performance adjustment apparatus and method of information processing apparatus

A data processing system comprising at least two operating systems (OS1, OS2) for virtual machines, a supervisory operating system, i.e., a control program (CP) for controlling the operating systems, control registers (CR0, CR1, ---) and an extended control register (ECR) having a special bit. When a control register operating instruction (LCTL or STCTL) is executed by one of the operating systems, the special bit has a first value and the operating system directly accesses the control register. When the other of the operating systems attempts to execute such a control register operating instruction, the special bit has a second value and an interruption is generated in the supervisory operating system.

System for directly and indirectly accessing control registers by

A main storage access control system for a virtual computing function system includes an address register for registering memory addresses used for accessing a main storage and being operated under a plurality of address modes having different effective bit lengths concerning the memory addresses, a tag register for registering tag bits for individually designating the address registers, and a selection unit for selecting the designation of address registers designated by the tag bits by means of an operand address of an instruction which is to be executed by the program of the virtual machine monitoring region. The address mode is changed to the address mode used by the virtual computing function system by means of the output signal of the selection means. The method concerning the conversion of an access key by the output of a register designation detection unit in a virtual computing function system is also treated.

Main storage control system for virtual computing function system with

A multiprocessor system including firmware, which system is comprised of at least a plurality of central processing units and a main memory to be commonly occupied by all the central processing units. The main memory is composed of an operating system area and a firmware area. The firmware area is divided into a common firmware area utilized by all the central processing units and a plurality of independent prefix areas allotted to the central processing units. Each prefix area is operative as an interface port, for a respective central processing unit, between the operating system area and the common firmware area.

Multiprocessor system including firmware

This invention relates to a register and more specifically to register control in a data processing system. In general, a number of control registers are theoretically required that is less than the maximum number which can be designated, and only the required number of registers are mounted as hardware. In order to add functions or to provide compatibility with other systems, it is sometimes required to use a register that is not mounted as hardware, or to use the registers mounted as hardware for conflicting purposes. Virtual registers are accordingly provided for at address locations in the memory of the processing system. However, if only the registers to be added are thusly provided for in the memory, the instructions must be executed by distinguishing between register access and memory access, in accordance with register number, etc. Thus, this invention provides a number of virtual registers for instance equal to the number that can be designated. The controls are thereby simplified in accordance with the kind of instruction to be performed. Namely, when an instruction is the LOAD instruction, the same content is loaded into both real an virtual registers from a respective address of the memory, and when it is the STORE instruction, the content from a respective virtual register is stored into the respective address of the memory.

Register control processing system

In a data processing device comprising a main storage unit, a buffer storage unit, and an error check and correction circuit, when data held in the buffer storage unit contains a single-bit error, the data containing the single-bit error is moved out from the buffer storage unit by generating a predetermined number of addresses having the same number (memory sector) as the data containing the single-bit error. The data is then corrected by the error check and correction circuit, and the corrected data is stored in the main storage unit.

System for treatment of single bit error in buffer storage unit

A system for processing machine check interruption using a data processor which outputs a machine check interruption signal by detecting the generation of a machine check condition and which performs interruption processing on the basis of the machine check interruption signal. The data processor includes a specific code detector which detects a specific interruption signal among the machine check interruption signals, a signal converting circuit for converting the machine check interruption signal into a modified code signal when the interruption signal generated by the machine check interruption is the above-mentioned specific code, and a control portion which assumes a disabled-waiting condition in response to the modified code signal. The operation of the data processor is stopped by placing the control portion in a disabled-waiting condition when interruption of the above-mentioned specific code occurs.

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Kawasaki, Japan

Toshio Matsumoto