Yamaha Corporation

Toshio Maejima

Masao Noro

Nobuaki H Tsuji

Akihiko Toda

Yusuke Yamamoto

Masato Miyazaki

Masayuki Iwamatsu

Tatsuya Kishii

Hirotoshi Tsuchiya

Norihiro Kawagishi

Masayoshi Nakamura

Akihisa Himeno

Moritaka Iyoda

Akihiro Toda

A signal processing device includes: an amplifier, a bandwidth of which can be switched, and a controller which is configured to perform control to operate the amplifier in a wide bandwidth for a constant time after start of a signal input to the amplifier and then operate the amplifier in a narrow bandwidth thereafter.

Signal processing device and amplifier

An offset cancel circuit includes a first amplifying section, a second amplifying section, a third resistor connected between a non-inverting input terminal of the first amplifying section and a non-inverting input terminal of the second amplifying section, and a current source. In the offset cancel circuit, the current source causes a constant current to flow through the third resistor to cancel an offset voltage from output signals of first and second amplifying sections, the constant current corresponding to the offset voltage contained in first and second output signals output from a bridge resistance type sensor.

Offset cancel circuit

A voltage generation circuit includes a voltage detection circuit that generates a detection voltage according to an output voltage, a reference voltage generation circuit that generates a reference voltage which changes periodically, a comparison circuit that generates a control signal according to a result of a comparison between the detection voltage and the reference voltage, wherein control pulses each having a pulse width according to the detection voltage are sequentially appeared in the control signal, and a driving pulse generation circuit that generates a driving pulse corresponding to the control pulse and supplies the generated driving pulse to a transistor connected to a DC power source when the pulse width of the control pulse exceeds a predetermined width, and stops generating the driving pulse when the pulse width of the control pulse becomes smaller than the predetermined width.

Voltage generation circuit

A class D amplifier includes an amplifier that generates a digital signal for driving a load based on an input signal, an attenuator that attenuates the input signal according to an attenuation command signal, and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

Class D amplifier

A class-D amplifier for generating from an input signal a digital signal for driving a load, includes an output limit instruction generating section that detects that the digital signal falls outside a limit range and that outputs an output limit instruction signal, an attenuation instruction pulse generating section that includes an integrator for integrating the output limit instruction signal and that outputs a periodical attenuation instruction pulse having pulse width corresponding to an integrated value in the integrator, an attenuating section provided in an input path for the input signal and that attenuates the input signal based on the attenuation instruction pulse, and a mute control section that controls the integrated value in the integrator independently of the output limit instruction signal to control an amount of the attenuation of the attenuating section applied to the input signal.

Class-D amplifier

A voltage adder circuit includes an amplifier circuit having a first operational amplifier and into which a first voltage is input, a circuit that supplies an output current to the amplifier circuit, and a current providing section that detects the output current of the circuit and supplies an output current equal to the output current of the circuit in magnitude so that the output current of the circuit is prevented from inputting to or outputting from the first operational amplifier through an output terminal of the first operational amplifier. A second voltage is input into the circuit.

Voltage adder circuit and D/A converter circuit

A class D amplifier includes: an amplifier that generates a digital signal for driving a load based on an input signal; an attenuator that attenuates the input signal according to an attenuation command signal; and a clip prevention controller that outputs the attenuation command signal to intermittently attenuate the input signal when the digital signal is brought into a clip state or a near-clip state.

A PWM modulator adds first and second input signals to each other, and performs PWM modulation processing for outputting a PWM-modulated pulse whose pulse width is modulated according to a result of addition. A shift register delays a bit stream acquired from a &#x394;&#x3a3; modulator, thereby generating two bit streams having a time difference which is one-half a period of PWM modulation processing, and the bit streams are supplied at first and second input signals to the PWM modulator.

PWM signals having different polarities input from a +IN terminal and a &#x2212;IN terminal are output to a pre-driver and a switching signal generation circuit. The pre-driver outputs to switches a gate signal for actuating a driver obtained from the input PWM signal. The switching signal generation circuit inputs a PWM signal and outputs switching signals. A switching circuit, on input of the switching signals, changes over switches so that the gate signal is output to a first P-channel MOS transistor and a first N-channel MOS transistor in case the PWM signal is input from the +IN side, and to a second P-channel MOS transistor and a second N-channel MOS transistor in case the PWM signal is input from the &#x2212;IN side.

Amplifier

An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics. A full-wave rectifier, applicable to the amplitude adjustment device, is mainly configured by an inversion amplifier, an amplifier and an output section. Herein, the inversion amplifier amplifies an input signal with a gain of '&#x2212;1', while the amplifier amplifies it with a gain of '1'. Outputs of the amplifiers differ from each other in phases by 180&#xb0;. The output section produces a full-wave rectified signal based on the outputs of the amplifiers. Incidentally, all of the amplifiers and output section are configured using field-effect transistors without using diodes being externally connected. Hence, it is possible to manufacture the full-wave rectifier in a form of an IC in accordance with the MOS process with ease.

Device for amplitude adjustment and rectification made with MOS technology

A class-D amplifier for pulse-width-modulating an analog input signal to output a pulse-width-modulated signal, includes: a differentiating circuit for differentiating the pulse-width-modulated signal of the class-D amplifier; and a negative feedback circuit for feeding back the differentiated signal of the differentiating circuit to an input side of the class-D amplifier in a negative feedback manner.

A class-D amplifier includes: an operational amplifier and capacitors, which constitute an integrator for integrating a difference between a plus-sided input signal and a minus-sided input signal which constitute analog input signals; delay circuits for delaying a phase of a triangular wave by a desirable very small angle; resistors, which constitute a synthesizing circuit for synthesizing an output of the integrator, the triangular wave, and outputs of the delay circuits with each other; comparators for comparing outputs of the synthesizing circuit with each other; AND circuits which constitute a buffer for inputting outputs of the comparators; and resistors feeding back an output of the buffer to an input side of the integrator.

A pulse width modulation (PWM) amplifier which is capable of reducing unwanted radiation from a PWM output thereof, which can cause EMI, while reducing manufacturing costs thereof. A triangular wave-generating circuit () of the PWM amplifier outputs a triangular wave. The triangular wave has a waveform steep or gentle in pulse rising and falling slopes dependent on a value of current flowing through an FET () or an FET (). The value of current is changed by a current flowing through a FET (). A switching element () changes voltage applied to the gate of an FET (), for control of increase and decrease in the current flowing through the FET (). This enables the triangular wave to be generated such that it is formed by pulses having different periods. An input signal is subjected to PWM amplification based on the triangular wave generated.

Pulse width modulation amplifier

A signal level shift circuit is provided for different circuit systems operating based on different supply voltages (VDDL, VDDH), wherein a supply voltage detection circuit detects a reduction of a first supply voltage (VDDL) regarding an input signal (IN). A level shift circuit comprises a load circuit portion consisting of PMOS transistors and a drive circuit portion consisting of NMOS transistors, all of which are connected together to form current paths. A switch circuit arranged for the current paths opens when a reduction is detected in the first supply voltage so that both the NMOS transistors are turned on. Thus, it is possible to effectively avoid occurrence of through currents flowing in the level shift circuit. The level shift circuit is followed by a flip-flop, which provides an output signal (OUT) in conformity with a second supply voltage (VDDH).

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Iwata, Japan

Toshio Maejima