Nec Corporation

Other

Toshio Komuro

Hiroaki Yokoyama

Shinichi Kuwabara

Takeo Fujii

Kazuo Shibata

Masaru Ushiroda

Tomohisa Abe

A method for treating or preventing a thrombosis in a person in need thereof comprising disposing in or on an article an effective antithrombotic amount of a composition and providing the article to be in close proximity to the skin of the person, the composition comprising (i) alumina, (ii) at least one substance selected from the group consisting of silica and titanium oxide and (iii) at least one element or compound selected from the group consisting of platinum, a platinum compound, palladium, a palladium compound, iridium, an iridium compound, rhodium and a rhodium compound.

Method for treating a thrombosis

A semiconductor memory in which a layout margin at the contact hole between wiring layers of a SRAM does not need and the wiring capacity at bit lines is reduced and the high speed processing is made to be possible is provided. The SRAM is constituted of a pair of driving transistors Qd,and Qd,, a pair of transferring transistors Qt,and Qt,, high resistance loads R,and R,, a pair of bit lines BL,and BL,, and a VCC line and a GND line. Gate electrodes of each transistor and word lines are formed at a first layer, the high resistance loads are formed at a second layer, the VCC line and the GND line are formed at a third layer, and the bit lines are formed at a fourth layer. A shared contact hole using for connecting the high resistance loads to the source/drain area of transistors does not penetrate the other conductive layers. Therefore, the layout margin between the shared contact hole and the other conductive layers becomes unnecessary and the reduction of the cell size becomes possible.

Semiconductor memory and manufacturing method thereof

A gate electrode is formed on a first conductive type semiconductor. Next, a second conductive type first impurity is selectively introduced in a drain formation planned region at a surface of the semiconductor substrate to form a first diffusion layer. Then, a second conductive type second impurity having a diffusion coefficient smaller than that of the first impurity is selectively introduced in a source formation planned region at the surface of the semiconductor substrate to form a second diffusion layer. Thereafter, a side wall is formed on a side surface of the gate electrode. Then, a second conductive type third impurity is introduced at the surface of the semiconductor substrate at a density higher than the first and second impurities, using the gate electrode and the side wall as a mask.

Semiconductor device having LDD structure and method for producing the same

A multi-input semiconductor logic device capable of high-speed operation includes a first to fifth source/drain regions formed in an active area, and first to fourth gate electrodes formed over the active area through a gate insulating layer. The first to fifth source/drain regions are arranged along an axis of the active area. The second and fourth source/drain regions are located to be adjacent to the first source/drain region at each side of the first source/drain region. The third and fifth source/drain regions are located to be adjacent to the second and fourth source/drain regions, respectively. The first gate electrode is located between the first and second source/drain regions. The second gate electrode is located between the first and fourth source/drain regions. The third gate electrode is located between the second and third source/drain regions. The fourth gate electrode is located between the fourth and fifth source/drain regions. The first and fourth gate electrodes are electrically connected to be applied with a first digital input signal. The second and third gate electrodes are electrically connected to be applied with a second digital input signal. The third and fifth source/drain regions are electrically connected.

Multi-input semiconductor logic device with mask pattern for reduced

In a method for manufacturing a BiMOS device, first and second semiconductor layers are formed on a semiconductor substrate, first and second field insulating layers are formed by using a LOCOS process on said first and second semiconductor layers, respectively. The first field insulating layer partitions a bipolar transistor area and a MOS transistor area, and the second field insulating layer is formed on a base-emitter junction region of the first semiconductor layer. Then, impurities are introduced via the second field insulating layer into the first semiconductor layer to form a base region therein. Then, an emitter opening is perforated in the second field insulating layer, and a polycrystalline silicon layer is formed on the second field insulating layer. Then, impurities of a first conductivity type are introduced into the polycrystalline silicon layer, and a heating operation is performed upon the polycrystalline silicon layer to form an emitter region. Then, the polycrystalline silicon layer is patterned to form an emitter electrode. Then, a gate insulating layer is formed on the second semiconductor layer, and a gate electrode is formed on the gate insulating layer. Finally, a base graft region is formed type in the first semiconductor layer and source/drain regions are formed in the second semiconductor layer.

Method for manufacturing BiMOS device with improvement of high frequency

A semiconductor static random access memory device has a memory cell array assigned a central area of a major surface of a silicon substrate and a peripheral circuit assigned a peripheral area of the major surface, and the memory cell array and the peripheral circuit are covered with a multiple-layered inter-level insulating structure; and the memory cells are associated with various conductive lines extending on different inter-level insulating layers, and dummy strips are inserted on the different inter-level insulating layers so as to make the multiple-layered inter-level insulating structure constant in thickness, thereby preventing a gate electrode of a component bulk transistor of the peripheral circuit from over-etching during formation of contact holes.

Semiconductor integrated circuit device with dummy pattern for

A semiconductor device with an LDD structure type MOS transistor is fabricated by forming a gate electrode on a semiconductor layer of a first conductivity type and a source/drain region in the semiconductor layer, the source/drain region having a high impurity concentration region and a low impurity concentration region of a second conductivity type. A pocket of the first conductivity type is formed in contact with the low impurity concentration region only on a drain region side and immediately under the low concentration region of the second conductivity type. The pocket formed only on the drain side can suppress the short channel effect and also the hot carrier generation without lowering the current capacity on the source side where no pocket is present.

Semiconductor device having LDD structure with pocket on drain side

A 'BiCMOS' semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

Semiconductor integrated circuit having bipolar and MOS transistors

In a method for manufacturing a 'BiCMOS' semiconductor integrated circuit, a gate oxide film 110 and a polysilicon film are grown on a semiconductor substrate, and after phosphorus is doped, the polysilicon film is patterned to form gate electrodes 112a and 112b and an emitter electrode 112c. A heat treatment is performed to form an emitter diffused region 113. Phosphorus and boron are selectively implanted with a low impurity concentration, respectively, to form a LDD N.sup.- region 114 and a LDD P.sup.- region 115. Thereafter, a side wall 116 is formed, and boron is implanted into areas B and C so as to form P.sup.+ source/drain regions 117 and a graft base region 18, respectively. Phosphorus is implanted to form N.sup.+ source/drain regions 119.

Method for manufacturing BiMOS device

In order to provide a multi-valued DRAM with an access time comparable to ordinary binary DRAMs, a potential difference generated by a memory cell between a pair of bit-lines is delivered to N-1 sets of sense amplifiers. Each delivered potential difference is shifted by a predetermined value for each sense amplifier for classifying the potential difference into N levels. A refreshing potential for the memory cell is obtained from outputs of the sense amplifiers activated with sense amplifier activating signals having potentials predetermined for each sense amplifier.

Multi-valued semiconductor memory device

A memory cell of a dynamic random access memory device is implemented by a series combination of a switching transistor and a storage capacitor connected between a bit line and a cell plate line, and a data bit stored in the storage capacitor produces a first potential difference indicative of the data bit between the bit line and another bit line paired therewith as well as a second potential difference between the cell plate of the storage capacitor and a cell plate line isolated therefrom, wherein a differential amplifier increases the second potential difference upon completion of a sense amplification on the first potential difference, thereby boosting the voltage level at the accumulating electrode of the storage capacitor while the bit lines and the cell plate line is being precharged again.

Dynamic random access memory device equipped with diferential amplifier

A built-in supply voltage dropping circuit according to the present invention includes a current mirror amplifier, a drive transistor with a gate connected to an output of the current mirror amplifier and a drain connected to the output terminal, and a current limiting device connected in series to the current mirror amplifier and adapted for controlling the current flow through the current mirror amplifier by control signals. This construction enables reduction of current consumption without lowering response speed.

Built-in supply voltage dropping circuit

A dynamic random access memory device has a plurality of one-transistor one-capacitor type memory cells each coupled between a first bit line and a second bit line paired with the first bit line, and parasitic capacitance coupled with the first bit line is approximately equal to a parasitic capacitance coupled with the second bit line so that a large potential difference takes place between the first and second bit lines when the storage capacitor is coupled with the first and second bit lines precharged to an intermediate voltage level.

Dynamic random access memory device having one-transistor one-capacitor

The semiconductor memory device according to this invention includes a memory cell array which comprises plural memory cells arranged in row and column direction in the form of an array, plural bit line pairs for connecting these memory cells in the unit of a column and word lines for connecting these memory cells in the unit of a row, sense amplifiers which are respectively connected to each of the bit line pairs at one end thereof and which amplify the potential difference between the bit lines of each pair in response to activation signals, and transfer gate means which divide said plural bit lines respectively into at least two portions corresponding to control signals, the sense amplifiers for the bit line pairs which belong to the nth columns (n is an odd numbered integer) thereof being arranged on one end of the bit line pairs and on the other end thereof for the those which belong to the (n+1)th columns. This construction of the device can prevent crosstalk which would otherwise caused between adjacent bit line pairs immediately after the sense amplifiers are activated.

Growing community of inventors

Tokyo, Japan

Toshio Komuro