Mitsubishi Denki Kabushiki Kaisha

Toshio Kishi

Yukihiko Shimazu

Souichi Kobayashi

Toru Shimizu

Shunichi Iwata

Yuichi Nakao

Shigeo Mizugaki

Toshio Doi

A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300), and a second clock signal (S11) passes only through the selected delay element(s). That is, the second clock signal (S11) does not pass through the non-selected delay element(s), which reduces power consumption.

Digital delay circuit and digital PLL circuit with first and second

An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

Microcomputer for accessing a memory outside the chip by using an

A MOS integrated circuit comprising a middle potential node to which a middle potential is to be supplied, a first operation circuit operating between a first potential and the middle potential, a second operation circuit operating between the middle potential and a second potential, and a node stabilization circuit for stabilizing the potential of the middle potential node.

MOS integrated circuit with low power consumption

A semiconductor integrated circuit which converts power-supply voltage applied from outside into optimum voltage for operating an internal circuit at the frequency of an internal clock in response to a multiplication control signal supplied to a PLL circuit from outside to generate the internal clock for operating the internal circuit by dividing a clock supplied from outside or by judging the cycle of an internal clock generated by dividing an external clock so as to supply the optimum voltage to the internal circuit.

Growing community of inventors

Tokyo, Japan

Toshio Kishi