Socionext Inc.

Fujitsu Semiconductor Limited

Toshio Hino

Junji Iwahori

Tsuyoshi Sakata

Atsushi Okamoto

Hirotaka Takeno

Tomoyuki Yamada

Hideyuki Komuro

Tomoya Tsuruta

Katsuya Ogata

Yutaka Mizuno

Takanori Hiramoto

In a semiconductor integrated circuit device, a cell having no logical function placed in an end row of a plurality of cell rows includes: a third transistor opposed to a transistor of a cell adjacent in the Y direction; a third buried power line supplying VSS placed on the same side of the third transistor as the transistor of the adjacent cell; and a fourth buried power line supplying VDD placed on the opposite side of the third transistor from the transistor of the adjacent cell. The fourth buried power line is greater in size in the Y direction than the third buried power line.

Semiconductor integrated circuit device

A semiconductor integrated circuit device includes a clock buffer cell that is a standard cell transmitting a clock signal. The clock buffer cell has an input terminal and an output terminal. A first metal interconnect including the output terminal is located in a layer above a second metal interconnect including the input terminal and greater in width than the second metal interconnect.

A semiconductor device includes first and second power supply lines formed in a first wiring layer and extending in a first direction; third and fourth power supply lines formed in a second wiring layer, extending in a second direction, and connected to the first and second power supply lines, respectively; a fifth power supply line formed in the first wiring layer; and a first power switch circuit including a transistor provided between the first and fifth power supply lines. The transistor overlaps at least one of the third and fourth power supply lines. The first power switch circuit includes first and second wirings formed in the second wiring layer, extending in the second direction, not overlapping the third and fourth power supply lines, and connected to a source of the transistor and the fifth power supply line, and to a drain and the third power supply line, respectively.

Power supply line arrangement having power switch circuit

The present disclosure attempts to provide a capacitor cell having a large capacitance value per unit area in a semiconductor integrated circuit device using a three-dimensional transistor device. A logic cell includes a three-dimensional transistor device. A capacitor cell includes a three-dimensional transistor device. A length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the capacitor cell is greater than a length of a portion, of a local interconnect, which protrudes from a three-dimensional diffusion layer in a direction away from a power supply interconnect in the logic cell.

A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.

In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.

A plurality of gate electrode patterns to be laid out in parallel are alternately set as first patterns to be formed in a first exposure step of double patterning and as second patterns to be formed in a second exposure step. Subsequently, a circuit that includes transistor pairs each formed by connecting one of the first patterns and one of the second patterns in parallel is laid out. This reduces the risk of variations in characteristics of transistors caused by double patterning.

Layout method and method of manufacturing semiconductor device

A design support program stored in a recording medium readable by a computer includes acquiring a first analysis result including information about an area included in circuit information of a design target circuit and a second analysis result relating to a path of the circuit information, the temperature of the area being equal to or higher than a certain temperature; determining an arbitrary cell on a non-critical path from among cells arranged in the area as a target cell for decreasing the area temperature; and outputting a result of the determination.

Growing community of inventors

Yokohama, Japan

Toshio Hino