Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Toshio Fujisawa

Tomoya Sanuki

Nobuhiro Kondo

Kenichi Maeda

Jun Hasegawa

Keisuke Nakatsuka

Masayuki Miura

Toshitada Saito

Atsushi Kunimatsu

Shoji Sawamura

Shinichi Kanno

Takashi Maeda

Takashi Fukushima

Yasuhito Yoshimizu

Tatsuro Hitomi

Arata Inoue

Masahiro Okada

Hiroshi Maejima

Hiroshi Sukegawa

Tokumasa Hara

Daisuke Iwai

Shirou Fujita

Mie Matsuo

Kenji Funaoka

Keigo Hara

Reina Nishino

Masanobu Shirakawa

Kenichiro Yoshii

Takayuki Miyazaki

Hideo Kasami

Hitoshi Iwai

Xu Li

Naoto Oshiyama

Hideko Mukaida

Yuta Aiba

Masaki Unno

Tatsuo Shiozawa

Hitomi Tanaka

Daisuke Fujiwara

Yuji Izumi

Hiroto Nakai

Masanori Yamato

Shigenori Sugimoto

Ken Hamada

According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.

Nonvolatile memory, memory system, and control method of nonvolatile memory with command processing unit

According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.

Storage device and control method

According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.

Memory system

A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.

Semiconductor storage device and system

A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.

Semiconductor memory device

A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.

Storage system, memory chip unit, and wafer

According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.

Memory controller configured to transmit interrupt signal if volatile memory has no data corresponding to address requested from source

Nonvolatile memory, memory system, and control method of nonvolatile memory

A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.

Semiconductor storage device

A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of &#x2212;40[&#xb0; C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of &#x2212;40[&#xb0; C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.

According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.

Storage device and storage system including a memory to store a check code for an integrity check

According to one embodiment, the memory device includes a non-volatile memory, a volatile memory, and a controller. The controller carries out the transition to two different sleep states depending on a sleep instruction from the host device and saves sleep state information indicating the sleep state after the transition to the host-side storage device. Upon receiving a return instruction from the host device, the controller carries out return processing in accordance with the sleep state information stored in the host-side storage device.

Memory device, and information-processing device

Growing community of inventors

Yokohama, Japan

Toshio Fujisawa