Hitachi, Ltd.

Alaxala Networks Corporation

Toshio Doi

Takehisa Hayashi

Kenichi Ishibashi

Mitsuo Asai

Takeshi Takemoto

Yasuhiro Nakatsuka

Hiroshi Sakamoto

Akira Yamagiwa

Noboru Masuda

Tetsuo Nakano

Akira Misumi

Hisashi Ando

Ko Soeno

Tomio Iizuka

Akira Tanaka

Takeshi Aimoto

Kazuo Sugai

Nobuhito Matsuyama

Masayoshi Yagyu

Akira Masaki

Minoru Yamada

Toshihiro Okabe

Moritoshi Yasunaga

Takeshi Kumagai

Tetsuo Oyama

Testuo Oyama

Shunsuke Hino

Motoyuki Unno

Yuzo Hirai

Yukimasa Komahara

A relay device of relaying a communication packet is disclosed, which comprises: an input module configured to receive the communication packet as an input; a buffer configured to have a plurality of queues and temporarily accumulated the received communication packet; a sorter configured to sort the received communication packet to one of the plurality of queues, depending on a specific value obtained by a predetermined function that gives an aggregate output from an input which is transfer information regarding transfer of the communication packet; and a band controller configured to control a bandwidth for each of the plurality of queues and output communication packets accumulated in the plurality of queues for transmission of the communication packets. This ensures the quality of service, while saving the capacity of the buffer used for the queues.

Relay device and relay method

A network connection apparatus including: a plurality of line connection parts connected to network lines to transmit and receive packets; a transmission destination decision part for deciding a transmission destination on the basis of header information of a packet received by a first one of the plurality of line connection parts; a packet transfer part for transferring packets to a second line connection destination corresponding to the transmission destination decided by the transmission destination decision part; and, a power supply part for supplying power to the line connection parts and a power control part for controlling supply of power to each of the line connection parts from the power supply part.

Method of reducing power consumption of network connection apparatus and apparatus for same

A network routing device according to the invention transmits a packet via a second port based upon destination information included in the packet received via a first port referring to a routing table. In addition, the network routing device calculates beforehand a third port which is a transfer destination when a fault occurs in a destination connected to the second port. Further, the network routing device holds scenario information including a combination of the second port and the third port and updates the routing table based upon the scenario information when a fault is detected in either of the ports.

Network routing device and network routing method

The timing of digital signal sampling at a receiver is continuously adjusted relative to a master clock used to initiate sending, by controlling a phase difference between the receiver sampling clock and the master clock in accordance with feedback of an error signal determined by detecting deviation of sampling clock timing from desired reference timing during both start-up operation and normal operation. Propagation delay scattering in the individual devices is compensated for by setting the sampling clock at a desired reference timing at start-up. Propagation delay scattering caused by fluctuation during device operation is compensated for by detecting the deviation of the sampling clock timing from reference timing based on received digital signals during normal operation and then continuously correcting the sampling clock timing on the basis of the detection result.

Data transfer system and method

A first variable delay circuit delays the reception data from the transmitting unit which is outputted from an input buffer and generates the delayed data to a data unidentifying time detecting portion. First and second latches have latch timings at regular intervals before and after a latch timing of a third latch for receiving and outputting by second and third variable delay circuits, respectively. In an adjusting operation, delay amounts of the second and third variable delay circuits are fixed to a value which is sufficiently smaller than a transfer period, a delay amount of the variable delay circuit is increased, a judging circuit detects a preceding edge of the reception data, subsequently, the delay amounts of the second and third variable delay circuits are sequentially increased while maintaining to the same value, and a following edge of the reception data is detected. In this instance, the timing of the third latch is set to the optimum point of the maximum margin. In a normal operation, the judging circuit detects a deviation from the optimum point and the delay amount of the first variable delay circuit is finely adjusted in accordance with the detection, thereby maintaining the latch timing of the reception data at the optimum point.

Data transfer apparatus fetching reception data at maximum margin of

Data transfer system and method including tuning of a sampling clock

A method of controlling a cache memory disposed between a CPU and a main memory, wherein pairs of data and an address to be written in the cache memory are stored into a buffer memory. A plurality of pairs of data and an address read from the buffer memory are processed to compare the address fields thereof. Based on results of the comparisons, there is determined a write control for writing the data in the cache memory which has been subdivided into a plurality of banks. As a result, the plural pairs of data and an address are written into the plural banks of the cache memory, the addresses of the respective pairs being different from each other. With the provisions set forth above, the write operation can be independently conducted for each bank of the cache memory, thereby improving the write throughput.

Method and system for controlling cache memory with a storage buffer to

A processing apparatus of an integrated circuit structure for a multiprocessor system includes an execution unit operative on the basis of a virtual storage scheme and a cache memory having entries designated by logical addresses from the execution unit. For controlling the cache memory, a first address array containing entries designated by the same logical addresses as the cache memory and storing control information for the corresponding entries of the cache memory is provided in association with a second address array having entries designated by physical addresses and storing translation information for translation of physical addresses to logical addresses for the entries. When a physical address at which invalidation is to be performed is inputted in response to a cache memory invalidation request supplied externally, access is made to the second address array by using the physical address to obtain the translation information from the second address array to thereby generate a logical address to be invalidated. The first address array is accessed by using the generated logical address to perform a invalidation processing on the control information.

Method and apparatus for controlling one or more hierarchical memories

A semiconductor integrated circuit device is provided which include a plurality of cell columns each having a number of unit cells previously fabricated on a semiconductor substrate selected from the plural kinds of unit cells which are formed in desired circuits by electrically connecting circuit devices previously arranged. Each column includes at least one kind of unit cell of a dynamic circuit which has a node in a floating state during the operation of the cell unit. A fixed potential shield layer is also provided on the cell columns so as to cover the nodes of the dynamic circuits. By virtue of this, a wiring area for electrically connecting the desired cell units can be located between the cell columns and above the shield layer. In other words, signal wirings in the wiring area can pass over the nodes of the dynamic circuits. without adverse parasitic effects. The unit cell can also be provided with a precharge circuit comprising a standard cell and an in-cell wiring layer. Further, clock input terminals of the unit cells which are provided with a precharge circuit can be divided into plural groups, with all of said clock input terminals belonging to the same group and having equal load capacitances being connected. Clock buffer cells can be provided for supplying clock signals to the clock signal wirings for each group.

Semiconductor integrated circuit apparatus and method for designing the

An information processing system includes a plurality of functional blocks (neurons) and a data bus for transmitting in common the outputs of the individual functional blocks (neurons). Data transaction among the functional blocks (neurons) is performed through the data bus on the time-division basis. For preventing the outputs from conflicting or competition, addresses are assigned to the individual blocks (neurons), respectively, so that only the functional blocks (neuron) having the own address designated by the address signal supplied through an address bus outputs data signal onto the data bus, while the other functional blocks (neurons) receive the information on the data bus as the signal originating in the functional block whose address is designated at that time point. The addresses are sequentially changed. During a round of the address signals, data are transmitted from given functional blocks (neurons) to other given functional blocks (neurons).

Information processing system

This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock and applying one of the multi-phase clock signals as the feedback signal described above to the first control loop.

High speed clock distribution system

A dynamic semiconductor logic circuit comprising a MOS FET logic section for effecting a high-speed logic operation in response to input logic signals after precharging of an output mode and internal nodes the logic section, a CMOS/BiCMOS output buffer section for outputting a result of the logic operation, and a noise suppression section for preventing erroneous operations without sacrificing the high-speed operation characteristic. The circuit, which is fabricated with 0.5-.mu.m-rule technology and operates at high speed with a low-voltage power source of 4.5 V or less, has a precharging section for precharging the output node and internal nodes of the MOS FET logic section and a noise suppression section for latching the output node of the logic section to the source potential by feeding back the output of an output buffer section in order to enlarge the soft error margin. The latching current is held at less than a predetermined ratio to maintain the high-speed operation characteristic.

Semiconductor logic circuit with noise suppression circuit

A semiconductor integrated circuit device is provided which includes a logic circuit utilizing an error detection code. The device has a first circuit train including a series connection of plural stages of operation circuits for receiving input data, performing predetermined operations while the input data propagates through the operation circuits and providing output data; a second circuit train including a series connection of plural stages of error detection code correction circuits for receiving error detection code input corresponding to the input data, applying corrections to the error detection code in correspondence to the operations in the operation circuits in the first circuit train, and outputting an error detection code corresponding to the output data; and at least one error detection circuit for performing a comparison and check of the output of the operation circuit in the first circuit train and the output of a corresponding error detection code correction circuit in the second circuit train. Also, the semiconductor integrated circuit device of this invention comprises a logic circuit incorporating therein an error detection function by doubling the circuits which comprise a logic circuit using the error detection code, doubled operation circuits having the same function and inputted with the same signal, and a comparison circuit for mutually comparing the outputs of the doubled operation circuits.

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Kokubunji, Japan

Toshio Doi