Nec Corporation

Toshio Baba

Junichi Fujikata

Masaki Ogawa

Tsutomu Ishi

Kikuo Makita

Takashi Mizutani

Keishi Oohashi

Toshitsugu Sakamoto

Keiichi Ohata

Jun Ushida

Hisao Kawaura

Fumiyuki Nihey

Hiroo Hongo

Yukinori Ochiai

Tetsuya Uemura

Masashi Mizuta

Yoshimasa Kurihara

Tsutomu Nakanishi

Tsunehiko Omori

An optical modulator according to the present invention is configured at least by a semiconductor layer subjected to a doping process so as to exhibit a first conductivity type, and a semiconductor layer subjected to a doping process so as to exhibit a second conductivity type. Further, in the optical modulator, at least the first conductivity type semiconductor layer, a dielectric layer, the second conductivity type semiconductor layer, and a transparent electrode optically transparent in at least a near-infrared wavelength region are laminated in order.

Optical modulator and method for manufacturing same

A Schottky photodiode includes a semiconductor layer and a conductive film provided in contact with the semiconductor layer. The conductive film has an aperture and a periodic structure provided around said aperture for producing a resonant state by an excited surface plasmon in a film surface of the conductive film by means of the incident light to the film surface. The photodiode detects near-field light that is generated by at the interface between the conductive film and semiconductor layer the excited surface plasmon. The aperture has a diameter smaller than the wavelength of the incident light.

Method for fabricating photodiodes

Photodiode and method for fabricating same

There has been a problem that micromiaturization causes increase of the resistance of wiring structure and degradation of electron migration resistance and stress migration resistance. The present invention provides a wiring structure of a semiconductor device having a low resistance even when the semiconductor device is microminiaturized, free of electron migration and stress migration, and having a high reliability and a method for manufacturing the same. A semiconductor device having a wiring or a connection plug made of a mixture of a metal and carbon nanotubes berried in a wiring groove or a via hole made in an insulating film on a substrate where a semiconductor chip is fabricated, and its manufacturing method are provided.

Semiconductor device and its manufacturing method

There are provided on a substrate a block layer having an electron affinity smaller than that of the substrate, a p-type strained superlattice structure having no lattice relaxation and operating as a generation region of spin polarized electrons and a surface layer for accommodating a bending portion of the energy band. The superlattice structure is formed of a multilayer in which a strained well layer and a barrier layer are alternately laminated plural times. The strained well layer has a lattice constant greater than that of the substrate and a thickness equal to or less than a wavelength of electron wave, and the barrier layer has a conduction band lower in energy than that of the strained well layer and a thickness such that an electron in the conduction band can transmit based on tunnel effect. A difference in energy between the band for heavy holes and the band for light holes is further widened in the valence band of the superlattice structure due to compressive stress in the strained well layer.

Spin polarized electron semiconductor source and apparatus utilizing the

The tunnel transistor of the present invention has either a junction structure wherein a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor having the reverse conduction type to that of the first semiconductor are connected on a substrate or a laminated layer structure comprising a degenerated first semiconductor having one conduction type, a non-degenerated second semiconductor and a degenerated third semiconductor of the reverse conduction type to that of the first semiconductor all laminated on a part of a substrate. The tunnel transistor further includes a fourth semiconductor layer formed on an exposed surface of the second semiconductor, having a forbidden band wider than that of the second semiconductor and containing an ionized impurity therein, a gate electrode formed on the fourth semiconductor layer, and a pair of electrodes individually forming ohmic junctions to the first and third semiconductors. Due to the construction, even when the gate voltage is 0, electrons or positive holes are induced in the surface of the second semiconductor, and a tunnel current can be flowed between the source and the drain. Since control of the tunnel current can then be preformed by applying a reverse bias voltage between the gate and the drain, the leak current of the gate can be suppressed.

Tunnel transistor and method of manufacturing same

Disclosed is a three terminal tunnel device exhibiting a tunneling of carriers in a forward direction. The device comprises an intrinsic semiconductor region, an n-type degenerate semiconductor source region abutting one side of the intrinsic semiconductor region, a p-type degenerate semiconductor drain region abutting an opposite side of the intrinsic semiconductor region, an insulation region separating the three semiconductor regions from a semiconductor substrate, and a gate electrode being provided over the intrinsic semiconductor region through an insulation layer, whereby voltage signals to be applied to the gate electrode permit controlling a carrier concentration at a surface of the intrinsic semiconductor region. The device permits controlling a tunneling current of a forward-biased degenerate p-n junction and a current-voltage characteristic manifesting a negative differential resistance with the gate voltage signals.

Three terminal tunnel device

A tunnel transistor comprises a semiconductor film (27) between a gate isolating film (17) and parts of first (13) and second (15) semiconductor layers which are formed in a substrate (11) to serve as source and drain regions with a spacer region left therebetween and covered with the semiconductor film. The gate isolating film is over the part of the first semiconductor layer and is made of either an insulating material or a semiconductor material, each of which materials should have a wider forbidden bandwidth than a semiconductor material of the semiconductor film, such as silicon dioxide, silicon nitride, or aluminium nitride, or gallium phosphide for silicon, or AlGaAs fox gallium arsenide. A source electrode is formed on an uncovered area of the first semiconductor layer. The semiconductor film forms a tunnel junction with the first semiconductor layer and an ohmic junction with the second semiconductor layer, which junction may be either a homojunction or a heterojunction. The transistor can be of a submicron order and is operable as either of depletion and enhancement types of producing a great drain current at a high speed when supplied with no netavite gate voltage and with a gate voltage.

Tunnel transistor comprising a semiconductor film between gate and

A heterojunction transistor has a first semiconductor layer of a semi-insulating or a low impurity concentration, a second semiconductor layer formed on the first semiconductor layer and made of such a semiconductor material that, in cooperation with the first semiconductor layer, a first energy recess for electrons and a second energy recess for holes are respectively formed at the bottom of the conduction band and at the top of the valence band to constitute a conductive channel, a third semiconductor layer formed on the second semiconductor layer and forming a PN-junction with the upper surface of the second semiconductor layer to inject carriers into the conductive channel, a control electrode for applying an input signal to the third semiconductor layer, and a ground and an output electrode formed on the second semiconductor layer on the opposite sides of the third semiconductor layer.

Heterojunction transistor having bipolar characteristics

The superlattice type semiconductor material has a multilayered structure of first layers of semiconductor containing impurities and having a thickness thinner than electron or hole wavelength and second layers of semiconductor free from impurities or insulator having such a thickness that electrons or holes may penetrate by tunneling effect, the first and second layers being alternately piled. Electrons or holes distribute uniformly over the entire of the multilayered structure to show a property of uniform semiconductor material.

Growing community of inventors

Tokyo, Japan

Toshio Baba