Fujitsu Corporation

Toshio Arakawa

Kenji Yoshida

Daisuke Miura

Shuji Yoshida

Masayuki Okamoto

Mitsuaki Nagasaka

Hiroyuki Honda

The present invention provides a method for designing LSI including a logic circuit equipped with a scan circuit without generating a hard-macro library for the scan flip flops constituting the scan circuit. According to the method, first netlist NLis converted into second netlist NLby adding scan circuit including scan flip-flops. Order data for connecting scan chain of the scan circuit is extracted from the second netlist NL. Such second netlist NLis converted into third netlist NLincluding only hard-macros, and the third netlist NLis laid-out by re-ordering the scan chain so that the newly generated order data for is stored temporally. Fourth netlist NLincluding scan circuit formed by scan flip-flops of soft-macros is generated on the basis of the stored order data, then the fourth netlist NLis converted into fifth netlist NLby substituting the scan flip-flops of soft-macros for standard cells of hard-macros. Finally the generated fifth netlist is laid-out without re-ordering the scan chain.

Design method for integrated circuit having scan function

In a layout method for an LSI having a plurality of cells, automated arrangement of cells is performed on the basis of a netlist, which has cells and connection data therefor, and timing conditions, and, once a timing optimization processing is performed so that a plurality of cells are arranged on a chip, global wiring processing is implemented and the wiring congestion rate is analyzed. In addition, in small regions where a wiring congestion rate is so high that detailed wiring processing is judged to be difficult, cell rearrangement processing is implemented. Next, detailed wiring processing is performed with respect to the cells which have been rearranged. The rearrangement of cells is performed only in small regions with a high congestion rate, with the result that the overall cell arrangement in which timing is optimized is not changed markedly, whereby it is possible to reduce the probability of wiring being impossible in the course of the detailed wiring processing.

LSI layout method and apparatus for cell arrangement in which timing is prioritized

Each binary carry logic circuit of half adder circuits other than that for the least significant digit comprises a transfer gate turned on when an input bit A is active and receiving a carry-in bit *C at its data input, and a transistor , turned on when the input bit A is inactive, connected between a power supply potential VDD and the data output of the transfer gate a signal on which is a carry-out bit *C . Transfer gates to of binary carry logic circuits other than that for the least significant digit are connected in chain, and are simultaneously on/off controlled by input bits A to A , letting the carry-in bit *C from the least significant digit propagate through the transfer gate chain at a high speed.

Logic circuit for fast carry/borrow

Disclosed is a method for automatic wiring design between block circuits of an integrated circuit, which performs an automatic connection between an inter-block wire disposed between a first circuit block and a second circuit block, and terminals formed along sides of the first and second blocks, the sides facing each other. The method comprises the steps of (S ) sorting the terminals according to the width thereof; and (S S ) selecting a terminal from the terminals in descending order of the width, and connecting between the selected terminal and an inter-block wire belonging to a same net as the terminal. In another embodiment, the method comprises the steps of (a) sorting the terminals, connected to a power supply wire, according to the value of electric current passing through the terminals; and (b) selecting a terminal from the terminals in descending order of the value of electric current and connecting between the selected terminal and an inter-block wire belonging to a same net as the selected terminal.

Growing community of inventors

Kawasaki, Japan

Toshio Arakawa