Other

Sharp Kabushiki Kaisha Corporation

Toshinori Ohmi

Tadao Takeda

Hiroshi Ban

Akihiko Nakano

Hironori Matsumoto

Hideyuki Unno

Eiji Yanagawa

Alberto Oscar Adan

Norihiro Tokuyama

An integrated semiconductor circuit device comprising a diode bridge circuit formed of a Schottky barrier diode and a periphery circuit formed of a MOS transistor which are formed on a single silicon substrate, wherein a Schottky barrier, which is a component of the Schottky barrier diode, is made of a silicide layer.

Integrated semiconductor circuit device having Schottky barrier diode

In the present semiconductor device, a chip with an LSI circuit is secured to a board (with the chip flipped) so as to be level. The LSI circuit on the chip is specified to operate normally only when the chip is level. Further, the back of the chip is processed so as to give stress to the chip. The chip has a reduced thickness of 50 &mgr;m or less (alternatively 30 &mgr;m to 50 &mgr;m). Therefore, when the chip is detached from the board, it deforms and is no longer level due to the stress, which prohibits the LSI circuit from operating normally. This way, the present semiconductor device ensures that no analysis can be conducted on the LSI circuit once the chip is detached.

Semiconductor device and method of manufacturing the same

A semiconductor device includes, on a protective film laminated on a circuit principal part, (i) a light blocking film provided so as to cover the circuit principal part, (ii) an aluminum oxide film provided so as to completely cover the light blocking film, and (iii) a light-blocking upper wiring provided on the aluminum oxide film. An attempt to exfoliate the light blocking film or the light blocking upper wiring causes the resistance-detection-use upper wiring to break or thin, thereby resulting in an increase in the resistance of the resistance-detection-use wiring. The increase in the resistance is detected by the resistance detecting circuit part, and malfunction or inoperativeness of the circuit principal part is caused in response of detection. By so doing, the circuit principal part can be protected from analysis.

Semiconductor device wherein detection of removal of wiring triggers impairing of normal operation of internal circuit

A semiconductor device in accordance with the present invention includes a semiconductor element chip pressed and secured on a distortion die-pad so that the semiconductor element chip, sealed inside a package, is held in a predetermined distorted state. The predetermined distorted state is preferably downward or upward warping. The semiconductor element chip operates normally in the distorted state, and does not operate normally when the semiconductor element chip is separated from the semiconductor device, and thereby released from the distortion and laid alone. This ensures that the semiconductor element chip is protected from circuit analysis.

After a field oxide film is formed on a P-type semiconductor substrate, ion implantation of boron is carried out with respect to a whole surface of the substrate so that a channel stopper layer is formed. Then, a MOS FET is formed in an active region of the semiconductor substrate. Subsequently, ion implantation of phosphorus is carried out, by using a gate electrode of the MOS FET and the field oxide film as a mask, so that impurity layers which have the same type of conductivity as that of the channel stopper layer and has a concentration lower than that of the channel stopper layer are formed right under the source/drain regions of the MOS FET between the source/drain regions and the channel stopper layer.

Semiconductor device and method of manufacturing same

A process for preparing a BiCMOS semiconductor device having a MOS transistor element and a bipolar transistor element both of which are constituted in an epitaxial layer of n-type conductivity formed on a substrate of p-type conductivity, which comprises applying, after the formation of said epitaxial layer, an impurity ion of high energy simultaneously to specific of said epitaxial layer under which a channel region of said MOS transistor element and an emitter region of said bipolar transistor element are to be formed, thereby forming highly doped impurity regions around the bottom of said channel region and around the bottom of a base region of said bipolar transistor element.

Growing community of inventors

Nara, Japan

Toshinori Ohmi