Hitachi, Ltd.

Hitachi Video Engineering, Incorporated

Mitsubishi Electric Corporation

Hitachi Automotive Engineering Co., Ltd.

Hitachi Video and Information System, Inc.

Hitachi Ltd., Hitachi Video Engineering, Inc.

Toshinori Murata

Toshiyuki Kurita

Ikuya Arai

Isao Nakagawa

Shigeo Matsuura

Masafumi Kazumi

Kenji Katsumata

Nobufumi Nakagaki

Shigeru Hirahata

Yumi Bando

Hiroshi Sekiya

Masato Sugiyama

Takanori Eda

Takumi Okamura

Yuji Ito

Masahiko Achiha

Shinobu Torikoshi

Sunao Suzuki

Takaaki Matono

Kazuhiro Kaizaki

Akihide Okuda

Takayuki Mori

Moriyoshi Akiyama

Yasutaka Tsuru

Satoru Takashimizu

Yuji Yamamoto

Keiro Shinkawa

Haruki Takata

Tadashi Kasezawa

Kazuo Ishikura

Tomomitsu Kuroyanagi

Tsutomu Noda

Noriyuki Yamaguchi

Masaharu Yao

Masanori Kamiya

Toshiyuki Sakamoto

Mitsuhisa Shinagawa

Sadao Kubota

Hiroshi Miyamoto

Nobutaka Hotta

Eisaku Akutsu

Kazuhiro Ooyagi

Kouichi Ishibashi

Shoji Kimura

Kenichi Fujiwara

Masaru Nanki

Katsumi Hishiyama

Takuzi Kurashita

Satoshi Imuro

Nobuhumi Nakagaki

A boundary position detection apparatus in which the position of an imageless part (containing no meaningful image information) lying at the upper part or/and the lower part of a picture is precisely detected from a video signal. A line decision circuit decides whether each of lines constituting the picture belongs to an image part (containing meaningful image information) or to the imageless part. A boundary decision circuit decides the boundary between the image part and the imageless part. A time integration circuit integrates the detected boundary positions temporally, and determines a final boundary position. A detection control circuit finds an image-part region from the final position, detects the average luminance of the region and controls the integrating time interval of the time integration circuit with the average luminance.

Apparatus for detecting position of featuring region of picture, such as subtitle or imageless part

A television signal receiving apparatus and method is provided having channel decode means for receiving a signal with a video signal, a sound signal, a data signal, and additional data multiplexed to perform tuning, demodulation, and error correction on the received signal and a demultiplexor for separating the multiplexed signal to output coded data of each of the video signal, the sound signal, and the data signal and for extracting service information as one of additional data. A storage device is provided for storing the service information extracted from the demultiplexor, together with a write controller for controlling writing into the storage device, and a read controller for controlling reading of the storage device according to a user command entered by a user. A source decoder is also provided for decoding the coded data outputted from the demultiplexor using the information outputted from said storage device to output the video signal, the sound signal, and the data signal. The storage device records the service information supplied from the demultiplexor, and the read controller performs control such that necessary data are read from the storage device as required by the user, thereby enhancing the speed of processing associated with the service information to provide a quick response to the user requirement. Also, the write controller can control storage such that only necessary information for the next processing operation is stored, thereby reducing the size of the storage device which is necessary.

Television signal receiving apparatus and method specification

Apparatus for detecting position of featuring region of picture, such as

An arrangement to automatically change between a scrambled digital data output and descrambled digital data output of a receiver by inserting a control signal conforming to a program provider's policy into a transmission signal. In a receiving side, a descrambler descrambles a channel-decoded signal, a demultiplexer demultiplexes the multiplexed signal from the descrambler into encoded video and audio data for output to a source decoder, and extracts the control information inserted in the transmitting side for output to a switch or CPU. The CPU decrypts a control signal from the control information extracted by the demultiplexer to determine whether the scrambled digital signal or descrambled digital signal is appropriate for output, and outputs a changeover control signal depending on the result of decryption. A switch selects the output of a scrambled digital signal from a stage prior to the descrambler, or a descrambled digital signal from a stage subsequent to the descrambler, depending on the changeover control signal from the CPU. Thereby, a scrambled digital signal output or descrambled digital signal output can automatically be changed over depending on a program provider's policy.

Digital broadcast transmitting and receiving system and transmitting and

An apparatus and a method for receiving television signals can display a television signal of a novel signal format, even at a low cost, without addition of any hardware. The apparatus and a method for receiving a television signal employs a data input unit for receiving video data encoded by any one format among multiple kinds of encoding formats, a video data memory for storing the video data from the data input unit, a decoding process program memory for storing multiple kinds of decoding process programs for decoding processes corresponding to received video data having multiple kinds of encoding formats, a programmable logic device which can vary the hardware constitution for the decoding process, a logic device varying unit for varying the hardware constitution for the decoding process, a decoding control unit for varying the circuit constitution of the programmable logic device via the logic device varying unit depending on the encoding format of the input video data and decoding the video data stored in the video data memory into a video signal which may be displayed depending on the decoding process program, and a display for displaying the decoded video signal.

Video decoder/converter with a programmable logic device which is

To provide an image which is matched with an aspect ratio of a screen of a display unit by compressing and enlarging the whole of the image to a desired size. A video signal is sequentially written into a field memory in response to a write clock from an input terminal. A clock generating circuit supplies the field memory with a read clock having a frequency which is about 4/3 times as high as that of the write clock. A vertical enlargement control circuit reads a video signal from the field memory with a line period corresponding to a magnification factor and inhibits writing to a one-line memory with the same period to provide a line delayed output for an output signal from the field memory. A vertical interpolating circuit generates a scanning line signal by an interpolation operation in accordance with a control signal from the vertical enlargement control circuit.

Television receiver capable of enlarging and compressing image

An image control apparatus includes a waveform equalizer, a distorted waveform extraction control unit, a noise reduction circuit, and an image quality control unit. The waveform equalizer receives an input video signal, equalizes the waveform of the video signal, and outputs the waveform equalized video signal. The distorted waveform extraction control unit detects a distorted waveform from the output of the waveform equalizer and controls the waveform equalizer to perform waveform equalization suitable for the input video signal. It also controls the noise reduction circuit and the image quality control unit in accordance with changes in the frequency characteristic of the video signal before and after waveform equalization to intensify the noise reduction for degrading the image quality, when the high frequency band of the frequency characteristic of the input signal has been lowered, and, conversely, to debilitate or stop the noise reduction for enhancing the image quality, when the high frequency band has been raised.

Image control apparatus for a television receiver

In a motion-adaptive television signal processor, a field as a reference for a moving picture signal includes a signal delayed by a frame memory or a field memory. A non-standard signal is beforehand processed so as to separate Y and C signals, and the signal thus processed is input to a motion-adaptive processor to thereby reduce a deviation in center of gravity between a still picture signal and a moving picture signal on the timebase to thereby suppress unnatural motion of the picture.

Image signal correction circuit and image signal processor using the

In a television receiver in which scanning for an incoming video signal is performed at a frequency n times as high as the input horizontal synchronous frequency by suitably controlling writing and reading on its video memory, the signals for writing and reading on the video memory unit are generated by a horizontal synchronization/deflection circuit. The horizontal synchronization/deflection circuit is arranged by having a clock generation/synchronous deflection circuit for generating reference signals to control the writing and reading on the video memory unit provided with a phase comparator such that a horizontal drive signal to drive a horizontal deflection circuit and a flyback pulse are brought in phase.

Television receiver with control of writing and reading of video memory

A sync generator which generates a reference horizontal synchronizing signal, a time difference detector which detects the time difference between the reference horizontal synchronizing signal and a horizontal synchronizing signal within a received television signal, and a variable delay circuit which responds to an output signal of the time difference detector to control the delay time and delay the received television signal are installed in a television receiver. When a plurality of horizontal synchronizing signals exist in one horizontal scanning period of the received television signal, the time difference between the horizontal synchronizing signal with the maximum amplitude and the reference horizontal synchronizing signal is detected, and the delay time of the received television signal is controlled in the variable delay circuit according to this time difference. As a result, the phase of the horizontal synchronizing signal with the maximum amplitude matches the phase of the reference horizontal synchronizing signal. Therefore, when changes in the receiving environment cause the signal strength of ghosts to become greater than that of an original signal and it becomes desirable to receive the ghost as a main signal in place of the original signal, it is possible to switch from reception of the original signal to reception of the ghost signal without resulting in distortion of synchronization.

Television receiver

A clock pulse generator has a first clock pulse generator for generating a burst lock clock pulse signal synchronized with a color burst signal contained in a video signal; a second clock pulse generator for generating a line lock clock pulse signal synchronized with a horizontal synchronizing signal contained in the video signal; a detection circuit for detecting whether or not the video signal is a standard signal; and a phase control circuit for synchronizing the phase of the line lock clock pulse signal with the phase of the burst lock clock pulse signal when the detection circuit determines that the video signal is a standard signal. The line lock clock pulse signal is supplied to a synchronizing signal generator, a selected one of the burst lock clock pulse signal and the line lock clock pulse signal is supplied to a signal processing circuit when the detection circuit determines that the video signal is a standard signal, and the line lock clock pulse signal is supplied to the signal processing circuit when the detection circuit determines that the video signal is a non-standard signal.

Clock pulse generator capable of being switched to process both standard

In a television receiver including a digital circuit processing an input video signal in a digital mode, a clock generating circuit applies a system clock signal to the digital circuit, and comprises a phase comparator to which a horizontal synchronizing signal is applied, a low-pass filter connected to the phase comparator, a voltage controlled oscillator connected to the low-pass filter to generate the system clock signal, a first frequency divider dividing the frequency of the system clock signal generated from the voltage controlled oscillator to generate a horizontal deflection drive pulse signal, and a second frequency divider connected to the phase comparator. The phase comparator, the low-pass filter, the voltage controlled oscillator, the first frequency divider and the second frequency divider constitute a single PLL circuit, and the system clock signal and the horizontal deflection drive pulse signal are respectively generated from the PLL circuit.

A digital television receiver includes a decision circuit for deciding whether an input television signal is a standard signal or a nonstandard signal. A first clock signal generator circuit for generating a first sampling clock signal synchronized with a color burst signal is provided in combination with a second clock signal generator circuit for generating a second sampling clock signal synchronized with a horizontal synchronizing signal. When the standard television signal is received, the television signal is processed by employing the first sampling clock signal. When the nonstandard television signal is received, the television signal is processed by employing the second sampling clock signal.

Digital signal processing circuit driven by a switched clock and used in

There is provided a detection circuit for TV receiver which includes a frame comb filter and a field comb filter and which generates a luminance signal or a chrominance signal by effecting addition or subtraction upon video signals of two frames adjoining each other included in the received TV signal. This detection circuit includes a synchronization separation circuit, an APC circuit, a frequency division circuit connected to the APC circuit, and a comparator circuit connected to the frequency division circuit. The frequency of the chrominance subcarrier signal is demultiplied by the frequency division circuit. The phase of the chrominance subcarrier signal thus frequency-divided is compared with the phase of the synchronizing signal separated by the synchronizing separation circuit. It is thus judged whether the received TV signal is a standard TV signal or a nonstandard TV signal.

Detection circuit for detecting standard television signals and

A motion detector for a chrominance signal which is used with a TV receiver equipped with a video signal motion detector. This motion detector for a chrominance signal has a delay element for delaying the chrominance signal of a video signal by 1 frame period, a subtracter for subtracting the output signal of the delay element from the input signal thereof, an absolute value conversion circuit to which the output signal from the subtracter is inputted, and a smoother circuit to which the output signal from the absolute value conversion circuit is supplied. If the chrominance signal of video signals on two consecutive frames are the same, the output signal of the subtracter becomes zero. If the chrominance signals of video signals on two consecutive frames are different, the output signal of the subtracter takes a positive or negative value. The negative value signal is converted into a positive value signal by the absolute value conversion circuit. A signal is outputted from the smoother circuit only when the chrominance signals of video signals on two consecutive frames are different. This outputted signal is a chrominance signal motion detection signal. The luminance signal contained in a video signal is removed from the video signal using a comb-type filter.

Motion detector for chrominance signal in TV receiver

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Yokohama, Japan

Toshinori Murata