Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Toshinori Maeda

Toru Kakiage

Yukiharu Uraoka

Masaya Sumita

Jiro Miyake

Kazushi Yamamoto

Yukio Iijima

Hiroyuki Yabuno

Hiroshi Kamiyama

Yoshiyuki Iwamura

Tomoharu Kawada

Fumio Nakatsuji

Yasuteru Maeda

Hidenori Akiyama

In a semiconductor integrated circuit, there is constructed a test expected value programming circuithaving an input/input-output padfor retrieving a ground/power-source signalfrom a ground terminalor a power source terminalconnected to the semiconductor integrated circuit, a switchfor selectively switching the outputting of the ground/power-source signalinputted via the input/input-output pad, and an expected value generation circuitfor generating a test expected value signalbased on a switch output signaloutputted from the switch

Semiconductor integrated circuit and system LSI having a test expected value programming circuit

For reducing time required for error correction in an error correction device, data are transferred from a buffer memory not only to a syndrome calculator but also to an error detector at the same time, and until the syndrome calculator detects an error-containing code, the error detector performs error detection in parallel with the syndrome calculation done by the syndrome calculator. During error detection after the error corrector corrects the error, mid-term results of the error detection obtained before an error-containing code is detected are used. Consequently, it becomes unnecessary to transfer all data from the buffer memory to the error detector, thereby making execution of an error detection process possible at a halfway point.

Error correction device

The present invention provides an apparatus and method for error correction that can directly performs the operation without deinterleaving read data, that has an increased parallel operation and performs at high-speed. An error correction apparatus comprises a plurality of syndrome operation circuits based on a parallel operation, and a second Galois field multiplication circuit for multiplying a syndrome operation result halfway through the operation by index compensating coefficients.

Method and apparatus for error correction

The present invention provides an error correction apparatus and an error correction method, which does not execute unnecessary syndrome operation and operation processing subsequent to the syndrome operation. A format interface judges whether an uncorrectable error is included in parallel with demodulation of received data, and outputs an error correction incapability detection signal when the uncorrectable error is included. The error correction circuit executes decoding of the error correction, including syndrome operation, for demodulated data from the format interface , suspends the syndrome operation when the error correction incapability detection signal is input, and terminates the error correction.

An error-detecting information adding apparatus transfers original data received from an external host apparatus to a memory and to an error-detecting code generating unit in one DMA transfer so that while the original data is transferred to the memory, an error-detecting code is generated. The error-detecting code generated by the error-detecting code generating unit is transferred from the error-detecting code generating unit to the memory.

Error detective information adding equipment

In the memory exclusive control device having a CPU-,accessible to both a common memory and first memory devices, the CPU-,is prohibited from accessing to the common memory device (,) during OFF state of an access permission flag, and when the access permissive flag ON is established by TCS (,), the gate of the access permitting unit (,) is opened to thereby permit the CPU-,to access to the common memory device (,). Thus, the memory exclusive control can be realized for transferring a desired program to be processed to the address space of the first memory device, allowing omission of a third memory device.

Memory exclusive control device and method therefor

A data input-output device includes a single memory, an input interface unit for storing data in the memory, an operation unit for fetching the data from the memory, for performing operations on the data, and for updating the data in the memory when necessary, an output interface unit for transmitting the data in the memory that has been operated on by the operation unit to outside of the device, and a bus control unit for setting a priority for each of these units and for controlling memory access by these units according to the priorities every time a predetermined number of bytes of data is transferred.

System for operating input, processing and output units in parallel and

In a test circuit of an integrated semiconductor device such as a memory, a parallel-input linear feedback shift register (LFSR) is used for both compressing data and comparing the obtained compressed value with an expected compressed value, thereby judging whether or not the integrated semiconductor device under test is normal. The parallel-input LFSR comprises a plurality of registers, a plurality of 2-input exclusive-OR gates placed in the stages previous to the respective registers mentioned above, and a feedback information generating means for generating feedback information from the output from the final-stage register and from the output from the register in a specified middle stage. In testing the integrated semiconductor device, the parallel-input LFSR compresses sequential sets of data from the integrated semiconductor device so as to obtain a compressed signature and then supplies the first input of the 2-input exclusive-OR gate placed in the leftmost position with the output from the final-stage register, while supplying the first inputs of the other exclusive-OR gates with the outputs from the registers in their respective previous stages. The second input of each of the exclusive-OR gates is supplied with an expected signature. Thus, the compressed value is compared with the expected compressed value at the respective exclusive-OR gates of the parallel-input LFSR.

Test circuit and test method of integrated semiconductor device

A luminescence amount detecting part detects a weak optical radiation which a transistor in a semiconductor integrated circuit emits owing to a hot carrier effect. An output thereof is image-processed by an image processing part. An information storage part stores information on a transistor width and information on a switching frequency at an execution of a test pattern into each transistor. A switching time calculating part evaluates a switching time of the transistor from respective outputs of the image processing part and the information storage part to output a result. Thus the switching time can be evaluated easily without a electron beam tester whose operation is complicated. A delay time can be evaluated by detecting a luminescence amount which changes depending on a gate voltage, instead of measuring a gate voltage.

Device for and method of evaluating semiconductor integrated circuit

The clock generator of this invention includes: an input shutoff control circuit for receiving a base clock and a reference clock and outputting a first signal and a second signal in response to a reset signal, a phase comparator for outputting a phase difference signal indicating a phase difference between the first signal and the second signal; a voltage control oscillator for outputting a frequency variable clock in correspondence with the phase difference signal; and a voltage fixing control circuit for controlling a voltage of the phase difference signal in response to the reset signal, wherein, when the reset signal is in a first level, the input shutoff control circuit: outputs the base clock to the phase comparator as the first signal and outputs the reference clock to the phase comparator as the second signal, and the voltage fixing control circuit holds the voltage of the phase difference signal, and when the reset signal is in a second level different from the first level, the input shutoff control circuit outputs two signals to the phase comparator as the first signal and the second signal, the phase difference between the two signals being substantially zero, and the voltage fixing control circuit fixing the voltage of the phase difference signal to a predetermined voltage at which the voltage control oscillator does not oscillate.

Clock generator and method for generating a clock

A microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met.

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Osaka, Japan

Toshinori Maeda