Nec Corporation

Renesas Electronics Corporation

Nec USA, Inc.

Toshinobu Ono

Masayuki Mizuno

Koichi Nose

Koichiro Noguchi

Yoshio Kameda

Rabindra K Roy

Tamaki Toumiya

A semiconductor test apparatus, semiconductor device, and test method are provided that enable the realization of a high-speed delay test. Semiconductor test apparatuses (-) include: flip-flops () each provided with first input terminal SI, second input terminal D, mode terminal SE that accepts a mode signal indicating either a first mode or a second mode, clock terminal CK that accepts a clock signal, and output terminal Q, the flip-flops () selecting first input terminal SI when the mode signal indicates the first mode, selecting second input terminal D when the mode signal indicates the second mode, and holding information being received by the input terminal that was selected based on the mode signal in synchronization with the clock signal and supplying as output from output terminal Q; and hold unitthat holds a set value and that provides the set value to first input terminal SI.

Semiconductor testing device, semiconductor device, and testing method

In a method of test pattern generation for logic circuits, a whole circuit is divided into a plurality of partial circuits for test pattern generation by distributed-processing. ATG (Algorithmic Test Generation) process is performed per each of the partial circuits based on the result of RTG (Random Test Generation) process. Also disclosed are a test pattern generation system performing the method, and computer readable media having program for the test pattern generation system to perform the method.

Method of generating test patterns for a logic circuit, a system performing the method, and a computer readable medium instructing the system to perform the method

A method of selecting circuit elements in a sequential circuit for partial scan testing relies upon analyzing and breaking reconvergence through the selected circuit element. Different types of reconvergences present in the circuit and their affect on the circuit testability are considered. Harmful reconvergence present in the circuit are broken by scanning a memory element present in the reconvergence path.

Partial scan testability utilizing reconvergence through sequential

Growing community of inventors

Kanagawa, Japan

Toshinobu Ono