Micron Technology Incorporated

Mitsubishi Denki Kabushiki Kaisha

Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Toshinao Ishii

Yasuhiko Tanuma

Takashi Iwamoto

Hisayuki Nagamine

Kazuo Kyuma

Masanobu Takahashi

Shigetoshi Nara

Wei Zhang

Wolfgang Banzhaf

Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth source/drain regions are brought into the same potential as each other.

Semiconductor device having transistors in which source/drain regions are shared

Apparatuses for providing pads included in external terminals of a semiconductor device are described. An example apparatus includes a memory cell array, a data queue (DQ) circuit, a data pad and a power pad. The memory cell array may include one or more memory cells. In a write operation, the data pad receives write data and provides the write data to the DQ circuit. The DQ circuit receives the write data and provides the write data to the memory cell array. In a read operation, the DQ circuit receives read data from the memory cell array and provides the read data. The data pad receives the read data from the DQ circuit and provides the read data. The power pad provides a power supply voltage. The data pad and the power pad are disposed across from each other with respect to the DQ circuit.

Semiconductor device layout for a plurality of pads and a plurality of data queue circuits

An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.

Apparatus comprising antifuse cells

Disclosed herein is an apparatus that includes: a first diffusion region having a rectangular shape and including first and second source/drain regions arranged in the first direction; a second diffusion region having a rectangular shape and including third to fifth source/drain regions arranged in the first direction; a first gate electrode extending in a second direction, and provided between the first and second source/drain regions and between the third and fourth source/drain regions; and a second gate electrode extending in the second direction, and provided between the fourth and fifth source/drain regions. The first and third source/drain regions are brought into the same potential as each other, and the second and fourth, source/drain regions are brought into the same potential as each other.

A semiconductor device includes: first and second circuit cell arrays extending in first direction; first and second power supply lines each extending in first direction and arranged over first circuit cell array, first power supply line being supplied with first power source voltage; third power supply line extending in first direction separately from second power supply line, arranged over second circuit cell array, and supplied with second power source voltage; first transistor coupled between second and third power supply lines; and first circuit arranged on first circuit cell array and operating on first and second power source voltages supplied from first and second power supply lines, respectively.

Semiconductor device based on power gating in multilevel wiring structure

A semiconductor device includes a reduced-power-consumption circuit block which includes first and second power lines, and a first circuit cell. The first circuit cell includes a first functional-element-free region. The first functional-element-free region includes a first driver circuit configured to connect and disconnect the first power line and the second power line.

Semiconductor device with reduced power consumption

A floating device is provided, which allows an entire robot main body to float at a site. Mounted on the floating device are an image sensor which captures image data of persons around the robot main body; an information processing device which recognizes a specified person based on the image data captured by the image sensor, calculates a position of the specified person, and outputs a control signal for moving the robot main body toward the position of the specified person; a propulsion device which moves, based on the control signal, the entire robot main body to a close position close to the specified person so that the robot main body can be seen by the specified person; and an image display device, which displays image information useful for the specified person using the site when the robot main body reaches the close position. The information can be supplied to a specified object in a bi-directional fashion.

Floating robot

An input pattern or two-dimensional pattern is associated and stored with use of associative matrices having the same size as that of an input pattern without converting it into one-dimensional pattern, wherein the associative matrices are generated from the input pattern so as to maximize the Hamming distance between state invariants which correspond to each different storage pattern, and thereby a power of categorization that corresponds to each storage pattern can be enhanced, thus increasing the storage capability and robustness.

Method of storing associative information and a device therefor

An information retrieval system retrieves stored information on the basis of incomplete or noisy retrieval key information within a realistic processing time. The information to be recalled is stored in neural network associative memory. Genetic algorithms are adopted to avoid a thorough retrieval of data in a huge breadth and depth of high-order space which must otherwise be searched due to ambiguity of retrieval key information. The information containing the given retrieval key is effectively sought. A processor employs a neural network. A memory is correctly recalled from partial inputs or inputs in which noise is extremely pronounced by repeating a sum-of-product operation of a firing pattern within a synapse coupling matrix and also threshold value processing.

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Tokyo, Japan

Toshinao Ishii