Semiconductor Components Industries, LLC

Toshimitsu Taniguchi

Takashi Ogura

Takashi Hiroshima

Peter Austin Burke

Dean E Probst

Mitsuru Soma

In one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench. The apparatus can include a source region segment of a first conductivity type disposed in a first side of the mesa region where the source region segment is included in a plurality of source region segments and where the plurality of source region segments are aligned along the longitudinal axis. The apparatus can include a body region segment of a second conductivity type disposed in a second side of the mesa region opposite the first side of the mesa region and having a portion disposed above the source region segment where the body region segment is included in a plurality of body region segments.

Method for forming transistor devices having source region segments and body region segments

Transistor device having a source region segments and body region segments

In a general aspect, a trench-gate field-effect transistor can include an active region and a termination region. The termination region can include a structure where a portion in which formation of a PN junction is prevented (e.g., a termination extension and one or more semiconductor mesas) is overlapped with a portion of the trench-FET that includes a boundary (edge, etc.) between trenches (or portions of trenches) lined with only shield (thick oxide) and trenches lined with a stepped-shield dielectric (SSO) structure (e.g., shield dielectric and gate dielectric). That boundary can be referred to an SSO edge. Prevention of PN junction formation (e.g., during a channel and/or body implant for the trench-FET), in the disclosed approaches, can be accomplished using a polysilicon layer to block formation of, e.g., a p-type layer, in a semiconductor substrate (e.g., an n-type semiconductor region, epitaxial layer, etc.).

Termination structures for trench-gate field-effect transistors

In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus includes a plurality of body region segments of a second conductivity type disposed in the side of the mesa region. The plurality of body region segments define an alternating pattern with the plurality of source region segments along the side of the mesa region.

In at least one general aspect, an apparatus can include a first trench disposed in a semiconductor region and including a gate electrode, and a second trench disposed in the semiconductor region. The apparatus can include a mesa region disposed between the first trench and the second trench, and a source region of a first conductivity type disposed in a top portion of the mesa region. The apparatus can include an epitaxial layer of the first conductivity type, and a body region of a second conductivity type disposed in the mesa region and disposed between the source region and the epitaxial layer of the first conductivity type. The apparatus can include a pillar of the second conductivity type disposed in the mesa region such that a first portion of the source region is disposed lateral to the pillar and a second portion of the source region is disposed above the pillar.

Growing community of inventors

Aizuwakamatsu, Japan

Toshimitsu Taniguchi