Sanyo Electric Co., Ltd.

Toshimitsu Taniguchi

Takashi Arai

Masashige Aoyama

Toshiyuki Ohkoda

Shinya Mori

Yoshinori Hino

Naoei Takeishi

Akira Suzuki

Hiroyuki Shinogi

Kazuo Okada

Shinzo Ishibe

Kazuhiro Yoshitake

Yutaka Yamada

Hiroyuki Suzuki

Shuichi Takahashi

Junji Yamada

Kazutomo Goshima

Katsuhiko Iizuka

Tomonori Mori

Hiroyuki Dobashi

Takayoshi Honda

Shigeyuki Furuya

Fumiko Shikakura

A semiconductor forming transistors on a semiconductor substrate includes a low concentration source/drain region formed in the semiconductor substrate, a high concentration source/drain region formed in the source/drain region, a gate electrode formed on the substrate through gate oxide film, a P type body region formed under the gate electrode and placed between the source/drain regions and, plug contact portions contacting the source/drain region and arranged in plural, and a source/drain electrode connecting to the source/drain region with contact through the contact portions.

Semiconductor device with parallel interconnects

This invention is characterized in that, a gate electrodeF formed on a P-type wellvia a gate oxide film, a high-concentration N-type source layer and a high-concentration N-type drain layerrespectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration N-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layerand respectively parted by a P-type body layer formed under the gate electrodeF are provided.

Semiconductor device and method of manufacturing thereof

A nonvolatile semiconductor memory device includes a plurality of memory transistors, a plurality of insulating layers disposed over the transistors, and a plurality of metal layers. Each of the metal layers is disposed on one of the insulating layers. The device also includes a plurality of metal plugs disposed over corresponding memory transistors. Each of the metal plugs filling in a contact hole formed in one of the insulating layers and electrically connecting the metal layers disposed on a top side and a bottom side of the corresponding insulating layer. A top metal layer of the plurality of metal layers is configured to provide bit lines that correspond to the memory transistors, the metal plugs are vertically aligned, and one of the insulating layers is configured so that whether one of the memory transistors is connected to a corresponding bit line is determined by whether a metal plug corresponding to the memory transistor exists in the insulating layer.

Nonvolatile semiconductor memory device

This invention offers a ROM in which a user can program his digital data. In a memory cell array of the ROM, in which a plurality of interlayer insulation layers and a plurality of metal layers (including a bit line which makes an uppermost layer) are alternately stacked over each memory transistor, an insulation layer is formed on a tungsten plug in a first contact hole provided in a first interlayer insulation layer. The ROM is programmed by writing digital data '1' or '0' in each of the memory transistors according to whether a dielectric breakdown of the insulation layer is caused by a predetermined programming voltage (high voltage) applied from the bit line.

An LDD structure and a silicide layer are formed without a reduction in thickness of a silicon substrate or a carbon contamination. Forming a spacer on a sidewall of a gate electrode is performed in two process steps, i.e. dry-etching and wet-etching. Also, a silicon nitride film used as a buffer film in injection of high dose of impurities is removed by wet-etching. As a result, the reduction in thickness of the silicon substrate and the carbon contamination can be prevented. In addition, variation in depth of the high and low impurity concentration regions and silicide forming region with locations on the wafer can be suppressed because of high selection ratio available with the wet-etching.

Manufacturing method of semiconductor device

The invention is directed to reducing of the number of steps in a BiCMOS process. A first N-wellA and a second N-wellB are formed deeply on a surface of a P-type semiconductor substrate. A first P-wellA is formed in the first N-wellA, and an N-channel MOS transistor is formed in the first P-wellA. The second N-wellB is used as a collector of a vertical NPN bipolar transistor. A second P-wellB is formed in the second N-wellB. The second P-wellB is formed simultaneously with the first P-wellA. The second P-wellB is used as a base of the vertical NPN bipolar transistor. An N+ emitter layer and a P+ base electrode layer of the vertical NPN bipolar transistor are formed on a surface of the second P-wellB.

Semiconductor device having MOS transistors and bipolar transistors on a single semiconductor substrate

Semiconductor device with smoothed pad portion

A substrate is provided having first and second formation areas. An oxide film is formed on both formation areas. An oxidation resistance film is then formed on the oxide film. The second formation area is masked by disposing a photoresist on the oxidation resistance film above the second formation area. The oxidation resistant film is removed from the first formation area and then the photoresist above the second formation area is removed. The oxide film above the first formation area is removed while using the oxidation resistant film above the second formation area as a mask. A first oxide film is formed on the first formation area followed by the removal of the oxidation resistance film above the second formation area. Subsequently, a second oxide film is formed on the second formation area. The first oxide film is designed to have thickness different from the second oxide film.

Semiconductor device manufacturing method

This invention is characterized in that, a gate electrode F formed on a P-type well via a gate oxide film , a high-concentration N-type source layer and a high-concentration N-type drain layer respectively formed apart from the gate electrode and a low-concentration N-type source layer and a low-concentration H-type drain layer respectively formed so that they respectively surround the N-type source layer and the N-type drain layer and respectively parted by a P-type body layer formed under the gate electrode F are provided.

A semiconductor device has a bump electrode formed on a flat surface of a passivation film of the device. The bump electrode is connected to a top wiring layer through a plurality of openings in the passivation film underneath the bump electrode, which are filled with a conductive material. The bump electrode is formed away from via holes, which connects the top wiring layer for the bump electrode and a lower wiring layer connected to source and drain layers of the device.

Semiconductor device and the manufacturing method thereof

A semiconductor device includes a gate electrode on a P type well through a gate oxide film , a heavily-doped N&plus; type source layer formed to be adjacent to the one end of the gate electrode , an N&plus; type drain layer formed apart from the other end of the gate electrode , a P type body layer below the gate electrode , and a lightly-doped drain layer formed in an area extending from below the gate electrode to the heavily-doped N&plus; type drain layer so that it is shallow at least below the gate electrode and deep in the vicinity of the heavily-doped N-type drain layer

Semiconductor device and method of manufacturing the same

In a semiconductor device having P type and N type wells formed bordering on a step on a P type semiconductor substrate, a first transistor (precise transistor) having a first linewidth is formed on the P type well in a step lower region while a second transistor (high-voltage transistor) having a second linewidth greater than a linewidth of the first transistor is formed on the N type well in a step higher region.

Semiconductor device and manufacturing method thereof

A P-channel type DMOS transistor includes heavily doped source/drain layers formed in an N-type well , a gate electrode formed on a channel layer located between the source/drain layers , an N-type body layer formed in the vicinity of the source layer, and a lightly-doped drain layer formed between the channel layer and the drain layer . In such a P-channel type DMOS transistor, a P-type layer is formed in the channel layer at the upper part of the N-type body layer . In this configuration, the driving capability of the P-channel type DMOS transistor can be improved.

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Gunma, Japan

Toshimitsu Taniguchi