Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Toshimitsu Ando

Masaaki Iwasaki

Tatsuo Higuchi

Tadaaki Isobe

Junji Nakagoshi

Satoru Watanabe

Shinichi Kato

Shigeo Takeuchi

Yoshio Kiriu

Hitoshi Abe

Patrick Hamilton

Yasuhiko Hatakeyama

Tsuguo Matsuura

Masato Ishii

Shigeko Yazawa

Osamu Arakawa

Takuya Iizuka

In a system in which data transfer interfaces respectively of apparatuses are connected via a bidirectional bus to each other, the availability ratio of the bus is improved. An apparatus to issue read and write requests includes a write buffer to store write data and a bus changeover unit to monitor an operation status of the bus for a read data transfer. The apparatus immediately sends a read request via the bus to a communication partner and then receives read data via the bus from the partner. A write request and associated write data are once stored in the write buffer. When a predetermined number of write data is accumulated, a data transfer direction of the bus is changed if the bus is not being used by a read data transfer to successively transmit the write requests and write data thereof to the partner.

Data processing system including apparatuses connected via a bidirectional bus to each other and data transfer method for use with the same

To reduce an overhead of the interrupt on a processor associated with packet send and receive control in a network, a packet send command chaining unit is provided. Based on the control field in each packet send command, a send node controls an interrupt request to the processor in the packet level and sends a packet set with the control information to a receive node. Based on the control field in the received data packet, the receive node controls a receive circuit interrupt request, thereby reducing the number of times the interrupt on the instruction processor is caused for each packet send and receive operation.

Method and apparatus in a computer system having plural computers which

A parallel computer system includes a plurality of processor units, a data transfer network for interconnecting the processor units, a synchronizing network for allowing program execution to be performed synchronously by the individual processor units, a connecting unit for connecting the individual processor units and the synchronizing network, and an input unit connected to the synchronizing network. The connecting unit connects selectively the individual processor units to the synchronizing network in accordance with information inputted via the input unit. With the parallel computer system, a program can be executed synchronously in parallel by using a desired number of processor units of those incorporated in the system, whereby availability of processor resources of the system can be enhanced.

Parallel computer system

A parallel processor system includes: a reception buffer pointer controller for generating an address of a reception buffer area in which a received packet is written and for checking whether there is no space area in the reception buffer area; a discard command bit capable of being set and reset by an instruction processor; a received packet discard judging unit for judging from the discard command bit and information supplied from the reception buffer pointer controller, whether the received packet is written, suspended, or discarded; and a reception controller for controlling to write the received packet in the reception buffer area in accordance with an judgement by the received packet discard judging unit. With this arrangement, even if there is no space area in the reception buffer area for storing a received packet or even if the received packet cannot be received because of a failure in the reception processor unit, the received packet can be discarded at the reception processor unit.

Processor unit for a parallel processor system discards a received

A memory control unit connected to a scalar processor having a buffer for storing a copy of block data of a main storage and a vector processor having a store requester for writing data into the main storage is disclosed. The memory control unit has a block valid memory having a one-bit valid bit for all blocks. The valid bit represents that the copy of the block data corresponding to said bit is in the buffer of the scalar processor. The memory control unit further has a block group valid table which has a block group bit for each block group. The block group bit represents whether any one of the block valid bits of the block belonging to the corresponding group is valid or not. When the vector processor stores the data into the main storage by the store requester, the memory control unit first searches the block group valid table to check whether the block group valid bit of the block group including the store address is valid or not. If it is valid, the memory control unit further searches the block valid memory to check whether the block valid bit of the block including the store address is valid or not. If it is valid, it invalidates the buffer of the scalar processor.

Memory control device with vector processors and a scalar processor

Frames of digital data each representing a single picture of a video motion picture display are handled in a computer system with an extended memory operating in parallel with a computer system instruction processor and main memory to bypass the computer system input/output processor for continuously outputting the video information on a real time basis. The outputted data may be recorded continuously at a constant data rate for an entire motion picture worth of information or actually displayed on the video display on a real time basis. The extended storage has a memory larger than the main memory, where all of the frame data is stored and read out in high speed bursts to a buffer that continuously reads the data out of the buffer for outputting. At least a start command and a starting address in the extended memory are contained within the main memory to be read out and decoded by the instruction processor and computer system memory storage control, for transfer to the extended memory, where they are used to start the program, which includes extended memory control words stored in the main memory, which control words are decoded and executed in the extended memory in parallel with the computer system instruction processor. Addresses of succeeding frames are generated and decoded and used for fetching entirely within the extended memory, for memory areas according to indirect addressing. The extended memory has external data transfer and internal data transfer registers that hold command words for respective transferring programs that may be operated in parallel, with conflict between external transfer and internal transfer being decided in favor of external transfer to assure continuous data outputting.

Information processing system

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Isehara, Japan

Toshimitsu Ando