Iwatsu Electric Company Ltd.

Toshimichi Shimatani

Yoshihiro Kawata

Masayuki Kawashima

Masaharu Kamigaki

Hideharu Omori

Nobuyasu Shiga

Hironobu Oshikata

Masataka Kawamura

A key telephone system for use in PCM telecommunications includes an office line communication units, an extension interface unit, a receiving unit, an extension communication unit, and an information transmitting and receiving unit. The system further includes a timing setting unit for setting the timings for transmitting and receiving information from and to each of the office line communication unit, the extension interface unit, the receiving unit, the extension communication unit, and the information transmitting and receiving unit in which downstream information, which is applied from the extension interface unit to a plurality of terminal units, contains a start bit, bits expressive of data information, and bits expressive of parity information in each of a plurality of frames, contains bits expressive of control information in at least one of the frames, and contains frame-synchronization information for achieving the synchronization of frames in at least one of the frames, and upstream information, which is applied from the terminal units to the receiving unit, contains the bits expressive of the data information, the bits expressive of the parity information, and the bits expressive of the control information, and one of the downstream and upstream information is sent in the former half of each of the frames, and the other thereof is sent in the latter half thereof.

Key telephone system

There is disclosed a data circuit-terminating equipment (DCE) which connects a start-stop synchronous data terminal equipment (DTE) which is not synchronized with a PCM transmission line having various speeds. Further the DCE can satisfy recommendations of the V25 bis of CCITT. The DCE includes a start-stop synchronizing circuit to deliver a sampled request-to-send signal RS, a sampled send data and to transmit a clear-to-send signal CS to the DTE, a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make the sampled send data match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE. In the DCE satisfying the recommendations, the demapping circuit ANDs a clear-to-send signal and bits indicating the synchronized state to send the clear-to-send signal, and a short line shorting the clear-to-send signal and a carrier detect signal is employed.

Data circuit-terminating equipment

There is disclosed a data circuit-terminating equipment (DCE) which connects an asynchronous data terminal equipment (DTE) with a PCM trnsmission line having various speeds. Further the DCE can satisfy recomendations of the V25 bis of CCITT. The DCE includes a PLL obtaining a clock from the line, a timing generator generating timings for circuits, a mapping circuit mapping to make data from the DTE match into the line speed, a sending register converting transmission speed of the mapping circuit output to send to the line at the instructed period, a receiving register receiving data from the line to deliver data with the required speed during the required period for the DTE, and a demapping circuit receiving the receiving register output to demap and send to the DTE. In the DCE satisfying the recommendations, the demapping circuit ANDs a clear-to-send signal and bits indicating the synchronized state to send the clear-to-send signal, and a short line shorting the clear-to-send signal and a carrier detect signal is employed.

A telecommunications network such as a key telephone system having n terminal devices such as telephone sets which are notionally divided into m groups, for the time division multiplex transmission and reception of m groups of n channels of data, where n is at least six and m is at least three. The invention particularly features a method of, and apparatus for, demultiplexing the multiplex data signal prior to reception by the terminal devices. The multiplex data signal is such that the n channels of data are assigned respectively to a set of n consecutive time slots making up one frame. Under the direction of a control circuit the multiplexed m groups of n channels of data are written onto m groups of n demultiplexing shift registers, respectively, at a relatively high speed. Then each group of shift registers are read at a relatively lower speed during each time interval from the end of the writing of the corresponding group of channels of data of one frame to the beginning of the writing of the same group of channels of data of the next frame. The shift registers serve the dual purpose of demultiplexing and compensating for the difference in the rate of data flow on their input and output sides.

Time division multiplex data transmission method and apparatus

A data transmission circuit is disclosed which is arranged so that when transmitting data and control signals of a terminal equipment accommodated in a transmission line of 64 Kbps channels through use of a multi-frame arrangement, the data is assigned to a required number of bits in a predetermined number of frames in the multi-frame or adjacent ones of the predetermined number of bits and at least one synchronization flag bit and various control signals are assigned to the remaining bits but a request to send signal and the synchronization being assigned to one of the remaining bits according to the logic OR of their succeeding sampled values, whereby data of different transmission speeds can be transmitted by the same circuit.

Growing community of inventors

Fuchuu, Japan

Toshimichi Shimatani