Mitsui Minings & Melting Co., Ltd.

Panasonic Corporation

Nissan Diesel Motor Co., Ltd.

Toshimi Nakamura

Yoshinori Matsuura

Atsushi Koike

Kiyoshi Yamagishi

Takenori Yanai

Tetsuro Sato

Masaharu Myoi

Takayuki Takahata

Toshiaki Kawanishi

Nozomu Kitajima

Kiyotaka Yanagi

Kenjiro Izutani

Hideki Matsunaga

Mitsuhiro Nishina

Mitsuo Yaguchi

Rintaro Ishii

Shinichi Inoue

Hajime Watanabe

Kenichi Hiraizumi

Hideshi Sekimori

Yasuhiro Seto

Tsutomu Makino

A method of manufacturing a multilayer wiring board is disclosed, the method being capable of separating a substrate without large local warpage of the multilayer wiring layer and thereby improving the reliability of connection in the multilayer wiring layer. This method includes providing a laminated sheet having, in sequence, a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer while interposing a second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.

Production method for multilayer wiring board

There is provided a laminate that can suppress the warpage of a laminated product when used for the manufacture of the laminated product. This laminate includes a float glass substrate having a top surface and a bottom surface; and a metal layer provided on the top surface side of the float glass substrate.

Multilayer body

A method for producing a semiconductor package, capable of effectively suppressing contamination of a chemical liquid and unintended peeling-off of a reinforcing sheet, is provided. This method includes providing a tacky sheet including a substrate sheet, and a soluble tacky layer and a banking tacky layer on at least one surface of the substrate sheet; making a first laminate including a redistribution layer; using the tacky sheet to obtain a second laminate having a second support substrate bonded to a surface on the redistribution layer side of the first laminate with the tacky layer therebetween; peeling off the first support substrate, pretreating the resulting third laminate; mounting a semiconductor chip on a pretreated surface of the redistribution layer; immersing the third laminate in a solution to dissolve or soften the tacky layer; and peeling off the second support substrate in a state where the tacky layer is dissolved or softened.

Semiconductor package manufacturing method, and adhesive sheet used therein

A method for producing a semiconductor package, capable of suppressing damage of a device, and dissolving or softening a tacky layer quickly to peel off a reinforcing sheet, is provided. This method includes: providing a tacky sheet including a soluble tacky layer, making a first laminate, obtaining a second laminate having a second support substrate bonded to the first laminate, peeling off a first support substrate to obtain a third laminate, mounting a semiconductor chip thereon to obtain a fourth laminate, sealing a right end surface and a left end surface of the fourth laminate with sealing members and immersing a lower end surface of the fourth laminate selectively in a solution, giving a pressure difference between an inner space and the solution to allow the solution to penetrate into the internal space and dissolve or soften the soluble tacky layer, and peeling off the second support substrate.

Semiconductor package manufacturing method

A glass carrier-attached copper foil is provided that can achieve a desired circuit mounting board that reduces separation of a copper layer at the cut edge even if the copper foil is downsized to dimensions enabling mount of a circuit, and has an intended circuit pattern with a fine pitch. The glass carrier-attached copper foil includes a glass carrier, a release layer, and a copper layer with a thickness of 0.1 to 3.0 &#x3bc;m. The glass carrier has, at least on its surface having the copper layer thereon, a plurality of flat regions each having a maximum height Rz of less than 1.0 &#x3bc;m as measured in accordance with JIS B 0601-2001 and a rough region having a maximum height Rz of 1.0 to 30.0 &#x3bc;m as measured in accordance with JIS B 0601-2001. The rough region has a pattern of lines that define the flat regions.

Copper foil with glass carrier and production method therefor

There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.

Multilayer circuit board manufacturing method

There is a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween, wherein an unoccupied region without the soluble adhesive layer is provided within a facing area where the reinforcing sheet faces the multilayer laminate; allowing a liquid capable of dissolving the soluble adhesive layer to infiltrate the unoccupied region to dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced to generate no large local warpage, thereby improving the reliable connection and the surface flatness (coplanarity) of the multilayer wiring layer. The used reinforcing sheet can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.

Provided is a method of manufacturing a circuit board involves: preparing a composite laminate including a support, a release layer, and a multilayered circuit board; disposing the composite laminate on a stage such that one face of the composite laminate is put into tight contact with the stage; and releasing the support or the multilayered circuit board from the release layer such that the support or the multilayered circuit board forms a convex face with a curvature radius of 200 to 5000 mm while the face of the composite laminate is kept in tight contact with the stage. The method according to the present invention can prevent the occurrences of defects, for example, breaking in the support and cracking and wire disconnections in the multilayered circuit board in manufacturing of circuit boards, such as coreless circuit boards, and ensure stable release of the support or the multilayered circuit board.

Wiring board manufacturing method

Provided is a method of manufacturing a multilayer wiring board, in which electrical inspection can be performed with accurate probing while warpage of a multilayer laminate is reduced. This method includes providing a laminated sheet including a first support, a first release layer and a metal layer; alternately stacking wiring layers and insulating layers on a surface of the metal layer, wherein an n-th wiring layer being the uppermost layer includes an n-th connection pad; bonding a second support having an opening on a surface, remote from the laminated sheet, of the multilayer laminate with a second release layer therebetween such that at least a part of the n-th connection pad is disposed within the opening; releasing the first support from the reinforced multilayer laminate at the first release layer; and putting conductors into contact with the n-th connection pads of the reinforced multilayer laminate to perform electrical inspection.

Method for manufacturing multilayer wiring board

A method of manufacturing a multilayer wiring board is disclosed, the method being capable of reinforcing the multilayer wiring layer and thereby improving the reliability of connection and the flatness on the surface of the multilayer wiring layer. The method includes providing a laminated sheet having a substrate, a first release layer and a metal layer; forming a first wiring layer on the metal layer; alternately stacking insulating layers and wiring layers on the laminated sheet on which the first wiring layer is formed to give a laminate provided with a multilayer wiring layer; stacking a reinforcing sheet on the laminate provided with the multilayer wiring layer at the side opposite to the laminate sheet, while interposing the second release layer; separating the substrate from the metal layer; and separating the reinforcing sheet from the laminate provided with the multilayer wiring layer to give the multilayer wiring board.

There is provided a high gloss electrodeposited copper foil which can be manufactured in a short time. The electrodeposited copper foil has a fraction of the areas occupied by the {100} plane deviating by 18&#xb0; or less from the &#x3c;001&#x3e; crystal orientation of 10% or more determined by analysis of the surface by electron backscatter diffraction (EBSD) and at least one surface of the electrodeposited copper foil has a glossiness G(20&#xb0;) of 1,500 or more, determined in accordance with JIS Z 8741-1997.

Electrolytic copper foil and manufacturing method therefor

There is provided a metal foil suitable for an electrode substrate for an electronic element, which makes it possible to suppress oxidation of the ultra-smooth surface and also prevent roll scratches when wound in a roll. The metal foil of the present invention is made of copper or copper alloy. The front surface of the metal foil has an ultra-smooth surface profile having an arithmetic mean roughness Ra of 30 nm or less as determined in accordance with JIS B 0601-2001. The back surface of the metal has a concave-dominant surface profile having a Pv/Pp ratio of 1.5 or more, the Pv/Pp ratio being a ratio of a maximum profile valley depth Pv to a maximum profile peak height Pp of a profile curve as determined in a rectangular area of 181 &#x3bc;m by 136 &#x3bc;m in accordance with JIS B 0601-2001.

Metal foil and electronic device

There is provided an electrode foil that can form an organic electroluminescent device having a high external quantum efficiency despite the presence of the organic nitrogen compound at the interface of a metal foil and a reflective layer. The electrode foil of the invention includes a metal foil made of copper or copper alloy and a reflective layer provided on at least one surface of the metal foil. The electrode foil has an organic nitrogen compound at the interface between the metal foil and the reflective layer in such an amount that the ratio of the number of counts on the C&#x2014;N bond to the total number of counts on the copper and the C&#x2014;N bond: CN/(CN+Cu) in the organic nitrogen compound is 0.4 or less determined by time-of-flight secondary ion mass spectrometric analysis (TOF-SIMS) of the interface.

Electrode foil and organic light-emitting device

There is provided an electrode foil, which can show superior light scattering, while preventing short circuit between electrodes. The electrode foil of the present invention comprises a metal foil having a thickness of from 1 &#x3bc;m to 250 &#x3bc;m, wherein the electrode foil comprises, on at least one outermost surface thereof, a light-scattering surface having a Pv/Pp ratio of 2.0 or higher, wherein the Pv/Pp ratio is a ratio of a maximum profile valley depth Pv of a profile curve to a maximum profile peak height Pp of the profile curve as measured in a rectangular area of 181 &#x3bc;m&#xd7;136 &#x3bc;m in accordance with JIS B 0601-2001.

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Ageo, Japan

Toshimi Nakamura