Denso Corporation

Toyota Jidosha Kabushiki Kaisha

Kabushiki Kaisha Tokai Rika Denki Seisakusho

Nippondenso Co., Ltd.

Toyota Jidosha Kogyo Kabushiki Kaisha

Toshimasa Yamamoto

Yukihiro Takeuchi

Yukihiko Watanabe

Jun Saito

Hiroyuki Wado

Narumasa Soejima

Kazuhiko Kano

Hidefumi Takaya

Yoshinori Ohtsuka

Hirokazu Fujiwara

Tomoharu Ikeda

Minekazu Sakai

Sachiko Aoi

Akitaka Soeno

Yasushi Kohno

Takao Iwaki

Nobuyuki Kato

Tadashi Hattori

Inao Toyoda

Masahiro Sugimoto

Makiko Sugiura

Kenichi Ao

Shinichiro Miyahara

Akihiko Teshigahara

Yasuho Kitazawa

Tetsuo Yoshioka

Tsuyoshi Ishikawa

Jun Morimoto

Eishi Kawasaki

Yasutoshi Suzuki

Shinji Mori

Yuichi Takeuchi

Eiichi Okuno

Hitoshi Iwata

Shigeyuki Akita

Tsuyoshi Fukada

Hitoshi Yamaguchi

Makoto Sekizuka

Tomonori Nagata

Yuji Nishimura

Toshiyuki Morishita

Seiichiro Ishio

Kenji Matsui

Minoru Murata

Takeshi Endo

Takuya Nezaki

Toshiki Isogai

Naohiro Suzuki

Takayuki Ando

Keisuke Imai

Hitoshi Takamatsu

Eiichi Kinaga

Hirotane Ikeda

Mamoru Mori

Kiyoka Matsubayashi

Kenichi Yokoyama

Hiroshi Muto

Yasutaka Watanabe

Yuuichi Takeuchi

Seiji Nishide

Yoshitaka Gotoh

Kimimori Hamada

Hiroyasu Ito

Junji Ohara

Takeaki Kato

Masakazu Terada

Shingo Izuchi

Akio Numazawa

Shigekazu Imanaka

Tomoyuki Shoji

Keiichi Katoh

Kenichi Nara

Kazuhiko Kanou

Kozo Shibata

Yukio Kagami

Kiyokazu Isomura

Tomoyuki Mizutani

Ryuuichirou Abe

A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.

Semiconductor device and semiconductor device manufacturing method

A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.

Semiconductor device

A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.

Semiconductor device and method for manufacturing the semiconductor device

Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.

Semiconductor device with front and rear surface electrodes on a substrate having element and circumferential regions, an insulating gate type switching element in the element region being configured to switch between the front and rear surface electrodes

In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.

Silicon carbide semiconductor device and method of manufacturing the same

A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.

Insulated gate type semiconductor device having floating regions at bottom of trenches in cell region and circumferential region and manufacturing method thereof

An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.

Insulated gate semiconductor device and method for manufacturing the insulated gate semiconductor device

An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.

Insulated gate type semiconductor device

A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.

Semiconductor device having element region and termination region surrounding element region

A semiconductor device includes a first semiconductor layer surrounding a bottom of the trench gate, a second semiconductor layer disposed along one of end portions of the trench gate in a longitudinal direction of the trench gate, one of end portions of the second semiconductor layer contacting the body layer and the other of the end portions of the second semiconductor layer contacting the first semiconductor layer, and a connecting layer, one of end portions of the connecting layer being connected to the body layer and the other of the end portions of the connecting layer being connected to the first semiconductor layer, the connecting layer contacting the second semiconductor layer, and the connecting layer being separated from the one of the end portions of the trench gate in the longitudinal direction of the trench gate by the second semiconductor layer.

A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.

Manufacturing method of silicon carbide semiconductor device

A switching element is provided having a semiconductor substrate. A trench gate electrode is formed in the upper surface of the semiconductor substrate. An n-type first semiconductor region, a p-type second semiconductor region, and an n-type third semiconductor region are formed in a region in contact with a gate insulating film in the semiconductor substrate. At a position below the second semiconductor region, there is formed a p-type fourth semiconductor region connected to the second semiconductor region and opposing the gate insulating film via the third semiconductor region and containing boron. A high-concentration-carbon containing region having a carbon concentration higher than that of a semiconductor region exposed on the lower surface of the semiconductor substrate is formed in at least a part of the portion of the third semiconductor region, positioned between the fourth semiconductor region and the gate insulating film, that is in contact with the fourth semiconductor region.

Switching element and manufacturing method thereof

A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

SIC semiconductor device and method for manufacturing the same

An SiC semiconductor device and a related manufacturing method are disclosed having a structure provided with a p-type deep layer formed in a depth equal to or greater than that of a trench to cause a depletion layer between at a PN junction between the p-type deep layer and an n-type drift layer to extend into the n-type drift layer in a remarkable length, making it difficult for a high voltage, resulting from an adverse affect arising from a drain voltage, to enter a gate oxide film. This results in a capability of minimizing an electric field concentration in the gate oxide film, i.e., an electric field concentration occurring at the gate oxide film at a bottom wall of the trench.

Silicon carbide semiconductor device and related manufacturing method

A pinion of a pretensioner is provided at a side of a torsion shaft, which side is opposite a side connected integrally to a spool via a sleeve. A base lock of a lock mechanism is connected to the pinion. Due to the lock mechanism operating, a leg plate side end portion of the torsion shaft is locked. In this way, due to operation of the pretensioner, the pinion, which is connected to a rotating portion of a sleeve, also is locked by the locking mechanism. Therefore, a piston of the pretensioner is not lowered, and internal pressure of a cylinder does not affect deformation of the torsion shaft.

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Ichinomiya, Japan

Toshimasa Yamamoto