Seiko Epson Corporation

Toshimasa Usui

Akihiro Fukuzawa

Shigenori Isozaki

An oscillator includes a package having a first side, a second side, a third side, and a fourth side, a resonator and an oscillation circuit disposed in the package, an output terminal arranged along the first side of the package, and outputting a clock signal generated by the oscillation circuit, and a control terminal arranged along the second side of the package, and supplied with a digital control signal adapted to update an operation state of the oscillation circuit.

Oscillator, electronic apparatus, and moving object

A differential signal output circuit is equipped with a first output stage including serially connected transistors QP and QN a second output stage including serially connected transistors QP and QN an input device that supplies two signals having mutually reversed phases to the gate of the first output stage and the gate of the second output stage, respectively, based on an input signal, and a current supply device QP that supplies specified drain current to the first and second output stages.

Differential signal output circuit

A clock generating circuit for generating a clock signal of which frequency is variable, has a delay circuit a selector and a control circuit The delay circuit has buffers to for delaying the input clock signal and output terminals A to D each of which outputs a clock signal delayed by a different delay time. The selector selects one of the output terminals in the delay circuit based on the output from the control circuit The control circuit supplies an output signal formed of a group of bits that is circulated in a predetermined cycle, to the selector A cycle in an output clock signals OUT sequentially outputted from the output terminal through the output terminals selected by the selector increases or decreases in accordance with the group of bits in the output signal. Thus, the frequency in the output clock signal OUT will vary to reduce EMI noise.

Clock generating circuit and semiconductor integrated circuit using the same

A clock generation circuit that generates multi-phase output clock signals which immediately follow any change in the period of an input clock signal. This clock generation circuit comprises a voltage-controlled oscillator ( ) that generates an output signal having a frequency that varies in response to a control voltage; a phase comparator ( ) that compares the phase of the input clock signal and the phase of the output signal of the voltage-controlled oscillator, to detect the phase difference therebetween; control voltage generation circuits ( ) that generate a control voltage corresponding to that phase difference; and a variable delay circuit ( ) that generates multi-phase output clock signals by delaying the input clock signal in accordance with the control voltage.

Clock generation circuit, serial/parallel conversion device and parallel/serial conversion device together with semiconductor device

A method of minimizing line capacitance for transmission lines in integrated circuits is presented to decrease the device performance problems of time delay and noise generation caused by capacitive coupling effects. The prime objective is to decrease the high line capacitance associated with such long length lines as clock lines, buslines and analogue signal lines as well as designated lines requiring low line capacitance. A procedure for applying CAD to such a design concept is also indicated. Although the present embodiments refer to transmission lines within one layer of an IC, the basic concept outlined is applicable also to multilayer designs.

Growing community of inventors

Chino, Japan

Toshimasa Usui