Kabushiki Kaisha Toshiba

Toshimasa Adachi

Shuji Abe

Katsuya Kudo

Hideki Oto

A tuner circuit comprising a first frequency conversion means 14 for converting a high frequency input signal into a first intermediate frequency signal according to a first local oscillation signal, a second frequency conversion means 19 for converting the first intermediate frequency signal from the first frequency conversion means 14 into a second intermediate frequency signal according to a second local oscillation signal, a first PLL means 24 for controlling the first local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal having a fixed frequency, a second PLL means 31 for controlling the second local oscillation signal so as to synchronize the phase of the signal with that of a reference oscillation signal. In the first PLL means 24, a phase comparison frequency is set to a frequency higher than a specified value. In the second PLL means 31, a phase comparison frequency is set to a frequency lower than a specified value.

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Kanagawa-ken, Japan

Toshimasa Adachi