Hitachi, Ltd.

Hitachi Device Engineering Co., Ltd.

Toshiko Koizumi

Hitoshi Kume

Kazuhiro Komori

Toshihisa Tsukada

Tetsuo Adachi

Toshiaki Nishimoto

Tadashi Muto

Satoshi Meguro

Hideaki Yamamoto

Takeshi Wada

Yoshiaki Kamigaki

Takaaki Hagiwara

Kiyofumi Uchibori

The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.

Non-volatile semiconductor memory device erasing operation

An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

Semiconductor memory device

Growing community of inventors

Kokubunji, Japan

Toshiko Koizumi