Seiko Epson Corporation

Toshiki Takei

Mitsuaki Teradaira

Tadayuki Okamoto

Tsutomu Kasai

Makoto Noguchi

Hiroaki Kasuga

Kenji Nariai

Efficient power conservation is enabled using a configuration having multiple processors. A printing device has a first processor unit that runs a program stored in a first memory, and a second processor unit that runs a program stored in a second memory, and has operating modes including a normal mode in which the first processor unit and the second processor unit operate according to a normal clock, and a first power conservation mode in which, after going to a state enabling the first processor unit to execute some processes of the second processor unit, the first processor unit operates according to the normal clock, and the second processor operates according to a slow clock having an operating frequency lower than the normal clock.

Information processing device, printing device, and control method of an information processing device

A liquid cartridge includes an ink cartridge having a first housing portion for containing a liquid and a waste liquid storage cartridge having a second housing portion for containing a waste liquid, and a rewritable nonvolatile storage portion which stores a first threshold, a second threshold, liquid amount information and waste liquid amount information. The first threshold indicates a near liquid end state in which the liquid in the first housing portion is near to end. The second threshold indicates a near full state in which the waste liquid in the second housing portion is near to full. The liquid amount information indicates a liquid amount of the liquid contained in the first housing portion. The waste liquid amount information indicates a waste liquid amount of the waste liquid contained in the second housing portion. The ink cartridge and the waste liquid cartridge are integrally formed.

Liquid cartridge with a storage memory

Liquid cartridge, printer, and method for controlling a printer with a liquid cartridge having integrated waste storage and memory

A power supply control apparatus for reducing the frequency of running a specific process in an electronic device when the device power turns on or off too soon after being turned off by monitoring the operating state of the power switch. When the power supply control apparatus detects an operation turning the power to the hybrid processing apparatusoff, the power supply control apparatus continues supplying power for as long as needed to complete a given shutdown process. However, if the power supply control apparatusdetects an operation turning the device power on again after the power supply stops but before reaching a predetermined reset voltage a reset and restart command is applied to the electronic device. More particularly, if an operation turning the power on again is detected during the period while the power supply is maintained to complete the shutdown process after the operation turning the power off is detected, the command restarts the electronic device without running a process normally run after start up such as a cleaning process in a printer.

Power supply control apparatus and power supply control method

A data processing system enables faster exchange of data between data processing units having a CPU, and simplifies the writing of a data exchange program for the data processing units. A data processing apparatushas a communication unitwith a first storage unitand a second storage unitThe first storage unitis used for sending data from the first data processing unitto the second data processing unitThe second storage unitis used for sending data from the second data processing unitto the first data processing unitData can therefore be asynchronously exchanged between the data processing units without coordinating control of CPU operations in the data processing units, and control of data communication between the data processing units is simplified.

Data processing apparatus and data input/output apparatus and data input/output method

Control data is efficiently serially transferred to a drive device for driving a motor without involving the CPU. Data buffers are allocated at specific memory addresses. An address decoder decodes a memory address output to the address bus and applies a write enable signal to the corresponding data buffer to write data to that data buffer by DMA transfer. When data is written to a data buffer, a sequencer circuit compiles control data, based on data in that data buffers, in a shift register, and serially transfers the control data one bit at a time on a serial transfer line synchronized to a clock.

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Okaya, Japan

Toshiki Takei