Matsushita Electric Industrial Co., Ltd.

Kuraray Co., Ltd.

Panasonic Corporation

Sumitomo Chemical Company, Limited

Toshiki Mori

Takashi Onishi

Shigeaki Suzuki

Kazuo Yamamoto

Yoshin Tamai

Haruyasu Yamada

Seiji Yamahira

Nobuo Oi

Kunitoshi Aono

Hiroshi Fujii

Yoshiji Fujita

Tsutomu Fujita

Yasuhiro Tomita

Ichiro Nakao

Reiji Segawa

Akihiro Kondo

Akira Asai

Takashi Fukumoto

Yasushi Okuda

Katsuji Ujita

Masakatsu Maruyama

Takayuki Tanaka

Yoshinori Odake

Keisuke Sakai

Kenichi Hasegawa

Kozo Nakao

Kunio Mayahara

Ichirou Nakao

Makoto Matsumoto

Tatsuya Miyatake

Toyoki Takemoto

Junko Sato

Jun Shibata

Hitoshi Suwa

Akifumi Kawahara

Manabu Komiya

Masahiko Kitayama

Tsuyoshi Kajiyashiki

Michio Takigawa

Satoshi Mimura

Tomonari Nakatani

Naoyuki Katayama

Nobusuke Kashiki

Disclosed is a nonvolatile storage system including: a memory block having a plurality of flash memories; a flash memory power supply circuit outside of the memory block; and a flash memory controller. The flash memory power supply circuit has a plurality of types of power supply circuits for process execution, the power supply circuits for process execution generating and supplying power at a plurality of voltage levels needed to execute processes in the flash memories. The flash memory controller monitors changes of the internal states of the flash memories by communicating with the flash memories, thereby controlling the power supply circuits for process execution and the flash memories.

Voltage control circuit for providing two voltages generated based on a parameter corresponding to an input signal

Process execution control based on the internal states of flash memories and power supply circuit information

[Problem] The present invention provides an industrially advantageous production method of a 6-halogeno-3-arylpyridine derivative in which cryogenic condition is not required, production step is short, and an isomer difficult to be separated is not produced as a by-product, [Solution] A production method of a 6-halogeno-3-arylpyridine derivative represented by the general formula (III) comprising: the first step reacting a 2,5-dihalogenopyridine derivative represented by the general formula (I) with a magnesiation reagent; and the second step reacting the product obtained from the above-described first step, in the presence of a palladium compound, with a halogenoaryl derivative represented by the general formula (II).

Production method of 6-halogeno-3-arylpyridine derivative

A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in rows and columns for holding information, each of the memory cells having a control gate; a plurality of word lines extending in a row direction, each of the word lines being connected to the control gates of the memory cells of a corresponding row of the memory cell array; a plurality of bit lines extending in a column direction and connected to sources or drains of the memory cells; a row decoder for selecting any of the plurality of word lines; a column decoder for selecting any of the plurality of bit lines; a charge pump circuit for generating a voltage higher than a supply voltage; and a first switch located in a connection path between the row decoder and the charge pump circuit.

Charge pump circuit, semiconductor memory device, and method for driving the same

A semiconductor memory, including word lines, bit lines, memory cells provided at intersections between the word lines and bit lines, and a sense amplifier for reading out what is stored in the memory cells, bit line selection means for selecting a bit line from among the bit lines; switch means for turning ON/OFF a current of the bit line selected by the bit line selection means; current generation means for generating a threshold current; means for extracting a differential current between the selected bit line current and the threshold current when a value of the selected bit line current is greater than that of the threshold current; voltage conversion means for converting the differential current to a voltage; and determination means for determining a magnitude relationship between the threshold current and the selected bit line current based on an output voltage from the voltage conversion means.

Semiconductor memory having function to determine semiconductor low current

A pull-out lower limit voltage for setting a voltage level when the gate voltage of the charge transfer transistor is pulled out is supplied to a reset circuit. In order to secure the breakdown voltage margin of the transistor and the capacitor used in a booster cell, a voltage which is not necessarily constant is used as the pull-out lower limit voltage. Accordingly, it is possible to provide a stabilized booster circuit in which an optimal gate voltage level of the charge transfer transistor can be set, overcharging can be suppressed, and the recovery time of the booster circuit can be shortened.

Booster circuit

In a semiconductor memory device operative to discharge residual charge in a read bit line in a read cycle, the bit line is in the reset state at all times except during read operation. The reset state of a bit line is canceled when selected and connected to a read circuit for read, and information stored in a selected memory cell is read via the selected bit line. Upon completion of the read of the memory cell, the selected bit line is disconnected from the read circuit and reset to thereby complete discharge of residual charge in the read bit line prior to read operation in the next cycle. This ensures that during read determination operation in the next read cycle, the potential of a selected bit line will not vary with the bit line residual discharge in the previous read cycle.

Semiconductor memory device, and read method and read circuit for the same

To provide a single-ended-output-type level shift circuit capable of improving an increase in a delay time according to a voltage level shift operation at low voltage and suppressing an increase in an area occupied by the circuit, first and second invertersandof a CMOS type in which a gate of each MOS transistor is individually driven are provided and the first inverteris used as a level converting unit. A voltage level of a first control signal CSoutput from an output node noof the first inverteris forcibly dropped down by a voltage dropping circuit CONTso as to accelerate the operation of the second inverter. As a result, the inversion of the level of an output signal of the first inverteris accelerated. Further, the balance between current capabilities of the individual transistors is optimized and, in particular, the sizes of the transistors constituting the second inverterare reduced so as to suppress an increase in a circuit area.

Level shift circuit

A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.

Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof

Charge is trapped into a charge trapping region of one of two reference cells so as to achieve a state equivalent to memory cell characteristics having a smallest amount of current. Charge is trapped into a charge trapping region of the other reference cell so as to achieve a state equivalent to memory cell characteristics having a largest amount of current. Currents output from these reference cells are averaged by a current averaging circuit, and the resultant average current is output as a reference current R_REF

Non-volatile semiconductor memory device

A copolymer of a strait chain &#x3b1;-olefin and a vinyl compound (I) represented by the general formula CH&#x2550;CH&#x2014;R, wherein R is a hydrocarbon group, the steric parameter Es of the substituent R is &#x2212;1.64 or less and the steric parameter B1 of the substituent R is 1.53 or more, an adhesive containing the same as an effective ingredient, and an laminate containing the adhesive.

Copolymer, adhesive containing the same and laminate

In a reference cell, first and second cellsandhaving the same structure as that of a memory cell are provided. A memory cell current IREFof the first cellis set to be a minimum value of a memory cell current after an erase operation. A memory cell current IREFof the second cellis set to be a maximum value of a memory cell current after a write operation. The read circuitcompares a memory cell current Icell with a current (IREF+IREF)/2 and outputs a comparison result. A current source for use in erase verification and write verification may be used in place of the first and second cellsand

Non-volatile semiconductor memory device and method for reading the same

A modified olefin-based copolymer produced by graft-polymerizing an alkenyl aromatic hydrocarbon and/or an unsaturated carboxylic acid or derivative thereof to an olefin-based copolymer containing repeating units derived from a linear &#x3b1;-olefin and/or ethylene copolymer of ethylene and repeating units derived from a vinyl compound (I) or (II) described below, and an adhesive containing the product as an effective ingredient, in which an adhesiveness to an adherend such as olefin resins (e.g. polyethylene, polypropylene) is further improved, are provided. Vinyl compound (I): a vinyl compound represented by the general formula CH&#x2550;CH&#x2014;R, wherein steric parameters Es and B1 of the substituent R are respectively &#x2212;1.64 or less and 1.53 or more. Vinyl compound (II): a vinyl compound represented by the general formula CH&#x2550;CH&#x2014;R', wherein a substituent R&#x2032; is a secondary or tertiary alkyl group.

Modified olefin copolymer

A copolymer of ethylene and a vinyl compound (I) represented by the general formula CH&#x2550;CH&#x2014;R, wherein R is a saturated hydrocarbon group, a steric parameter Es of the substituent R is from &#x2212;2.77 to &#x2212;1.64 and a steric parameter B1 of the substituent R is from 1.53 to 2.90, a molded article comprising the same, an adhesive comprising the same as an effective ingredient an laminate comprising the same.

Copolymer

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Osaka, Japan

Toshiki Mori