Fujitsu Corporation

Mitsubishi Heavy Industries Limited

Toshikazu Ueki

Takashi Yamamoto

Makoto Hataida

Takaharu Ishizuka

Yuka Hosokawa

Takeshi Owaki

Daisuke Itou

Atsushi Morosawa

Seishi Okada

Hideyuki Koinuma

Go Sugizaki

Takao Matsui

Kenta Sato

Futoshi Izumi

Takeshi Sakamoto

Hisao Ogawa

Takayuki Kinoshita

Hidekazu Osano

Yoshikazu Iwami

Jin Takahashi

Masaki Toda

Atsushi Morozawa

An abnormality detection unit provided in at least one node among a plurality of nodes included in an information processing apparatus detects abnormality in a data transmission path of data transmission using a shared memory area sharable in a single node and other node, which is included in the storage unit provided in the single node or other nodes. An error information generation unit provided in the single node generates error information, based on the abnormality detected by the abnormality detection unit, and generates an interrupt with respect to a processor within a self node. The processor provided in the single node performs recovery processing, based on the error information according to the interrupt.

Information processing apparatus, computer-readable recording medium, and control method

An information processing apparatus including a plurality of nodes. The each of the nodes comprises a processor, a storage device, and a storing unit that stores therein multiple pointer sets in each of which a write pointer indicating an address used when data received from another node is stored in the storage device is associated with a read pointer indicating an address used when the data is read from the storage device. The each of the nodes comprises a notifying unit that notifies a node corresponding to a transmission source of the data of a pointer identifier that indicates a pointer set. The each of the nodes comprises a retaining unit that retains the received data in the storage device in accordance with an address indicated by a write pointer in a pointer set indicated by the pointer identifier.

Information processing apparatus, arithmetic device, and information transferring method

A solenoid type electromagnetic valve is configured such that an attraction force arises between an attracting side face of a solenoid core power supply body and an attracted side face of an armature which is facing the attracting side face when a current is conducted through a solenoidal coil, while the attraction force is released between the attracting side face and the attracted side face when the current conducted through the solenoidal coil is cut off, wherein at least one plate member of nonmagnetic material comprising nonmagnetic stainless steel, aluminum alloy or ceramic material is fitted to the attracting side face of the solenoid core power supply body, and fluid insulation resin is filled therein, thereby the fluid insulation resin is solidified and secures the plate member thereto.

Solenoid type electromagnetic valve device

An interprocessor communication measurement system for an information processing apparatus having a plurality of processors which may send data to the other processors through a plurality of communication channels, includes a socket which is connected with communication channels and electrically connects a processor attached thereto with the communication channels, a measurement node which is attached to the socket in place of the processor and electrically connected with the communication channels, wherein the measurement node includes a routing unit configured to send data destined for any one of the other processors to the one of the other processors through the communication channels and an intercepting unit configured to intercept data sent through the routing unit, and a storing unit configured to store data intercepted by the intercepting unit of the measurement node.

Interprocessor communication measurement system

An arbitration method includes a first process to perform a path control to transfer data from physically plural input ports logically having plural virtual channels to an arbitrary one of the plural output ports, wherein only one channel is selectable at one input port at an arbitrary point in time, by performing an arbitration among the channels of each of the plural input ports according to an arbitrary arbitration algorithm other than a time-division algorithm, and a second process to perform an arbitration among the plural input ports according to the arbitrary arbitration algorithm. The arbitrary arbitration algorithm used in the first and second processes is switched to the time-division algorithm for a predetermined time in response to a trigger.

Arbitration method, arbiter circuit, and apparatus provided with arbiter circuit

A data transfer device includes a data transmitting circuit includes an error detection code generating unit generating an error detection code for detecting an error in the data, and a transmission unit transmitting the data and the error detection code together with retransmit enable information representing that corresponding data transmitted before the former data or transmitted next can be retransmitted, the data receiving circuit includes a reception unit receiving the transmitted data, the transmitted error detection code and the transmitted retransmit enable information, an error detection unit detecting the error in the received data based on the error detection code, an error data retaining unit retaining the data in which an error is detected when the reception unit receives the retransmit enable information, and an error data comparing unit that comparing the error detected data retained in the error data retaining unit with corresponding data that is retransmitted.

Data transfer device and control method of data transfer device

An information processing apparatus includes nodes having a first node and a second node each of which includes a processor and a memory in which at least a part of area is set as a shared memory area, and an interconnect that connects the nodes. The first node transmits communication data to be transmitted to the second node by attaching identification information used for accessing a memory in the second node. The second node determines whether or not an access to the shared memory area in the memory in the second node is permitted on the basis of the identification information that is attached to the communication data transmitted from the first node and identification information stored in a storing unit and used for controlling permission to access, from another node, the shared memory area in the memory in the second node.

Information processing apparatus and access control method

To prevent a decrease in performance of controlling a snoop tag. A queue is stored with REPLACE target WAY information and an index as an entry associated with a REPLACE request received from a processor, the index stored in the queue is compared with an index of a subsequent READ request, and, as a result of the comparison, a process based on the index-coincident READ request is executed with respect to the snoop tag corresponding to a content of a cache memory of the processor. Further, the REPLACE target WAY information of the READ request is replaced with the WAY information in the index-coincident entry within the queue.

Control device for snoop tag

A verification device includes a data verifying unit that verifies whether data in a packet has an error using a first or a second verification mode, a packet generating unit that generates a packet in accordance with a first packet generation mode or a second packet generation mode respectively corresponding to the first and the second verification modes, a failure monitoring unit that monitors a failure of a transmission line that requires a switching of the verification mode, a switching packet transmitting unit that transmits to a destination device, a switching packet for informing the switching of the verification mode used by the data verifying unit when the failure monitoring unit detects a failure or a removal of a failure, a generation mode switching unit that switches the generation mode, and a verification mode switching unit that switches the verification mode to the one informed by the switching packet.

Verification device, verification method, and verification program

The method for reconfiguring an information processing apparatus includes: transmitting, by the system management unit, a register setting request to set a register included in the control unit to a predetermined value to all of the system boards within the information processing apparatus, when a system board is added to or removed from any of the partitions; setting, by the system board that receives the register setting request, a register of a control unit of the local system board to the predetermined value, if a partition to which the local system board belongs includes the system board to be added or removed; and ignoring, by the system board that receives the register setting request, the register setting request if the partition to which the local system board belongs does not include the system board to be added or removed.

Information processing apparatus and method for reconfiguring the information processing apparatus

A northbridge, when detecting a synchronization break of a redundant CPU, stops the operation of an abnormal CPU bus where an error has occurred and the firmware in a firmware hub instructs the northbridge to inhibit an external instruction. In addition, the firmware saves the inside information of a normal CPU connected to a normal CPU bus and cache data on a memory and the northbridge issues reset to all CPUs in the home system board. The firmware then restores the inside information of the CPU saved on the memory to all CPUs and instructs the northbridge to cancel the inhibition of the external instruction.

Information processing apparatus for inhibiting instructions, saving and restoring internal information in response to abnormality in redundant processor system

A request issued by the CPU is output from the local arbiter by way of the CPU bus and the CPU-issued request queue. The cache replacement request loop-back circuit determines at the loop-back determination circuit whether the outputted request is a cache replacement request or not. A request other than a cache replacement request is output onto the local bus. A cache replacement request is output to the selector and sent to the request handling section when there is no valid request on the global bus.

Multiprocessor system, system board, and cache replacement request handling method

An information processing device having two processing units capable of operating in synchronization with each other, includes: a common unit capable of outputting an identical signal to the two processing units; detection units that are respectively provided for the processing units and each detects errors occurred in corresponding processing unit respectively; a comparison unit that compares outputs from the two processing units; and a control unit that controls signals from the processing units to the common unit, based on a detection result of the detection units and a comparison result of the comparison unit, and determines, if errors of an identical type are simultaneously detected by the detection units, that the errors are due to an error of the common unit.

Information processing device and error processing method

A control device managing a plurality of nodes transmitting and receiving data containing an error correcting code, comprises means accepting, when any one of the nodes detects an uncorrectable error from the data containing the error correcting code, a signal transmitted by the node detecting the error, means judging from a record of the detection of a first node, when accepting the signal from a second node receiving data transmitted by the first node, whether or not the first node has detected the uncorrectable error from the data transmitted to the second node, and means stopping, when the first node has detected the uncorrectable error from the data transmitted to the second node, a process attributed to the acceptance of the signal from the second node.

Node device, control device, control method and control program

In a system controller including a CPU-issued request queue having a circuit that processes plural requests having identical addresses not to be inputted to the CPU-issued request queue, a latest request other than a cache replace request is retained by an input-request retaining section. Consequently, even if an address of an issued request for cache replace request matches an address of a request retained by the CPU-issued request queue, the issued request for the cache replace request is not retried but is queued in the CPU-issued request queue when the address of the issued request for the cache replace request does not match the entire address retained by the input-request retaining section.

System controller, identical-address-request-queuing preventing method, and information processing apparatus having identical-address-request-queuing preventing function

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Kawasaki, Japan

Toshikazu Ueki